AXI4 burst and size: AWLEN and AWSIZE address stepping

What you practice

AXI4 burst and size: AWLEN and AWSIZE address stepping (3.1). Implement burst length and transfer size with AWLEN and AWSIZE address stepping. It is in AXI4 Burst and Size — Part 3 · AXI4 Full RTL Design of the AXI Masterclass. Burst, outstanding, and a BRAM memory bridge.

AXI only counts when the handshake simulates. RTL Studio is the Verilog and SystemVerilog IDE where you edit the RTL and prove each beat on a VCD.

Run it in the Verilog IDE

1. Open the lesson in the IDE and find the valid/ready or AXI channel ports in the editor.
2. Simulate with Verilator. Confirm the beat on the VCD, not only in the transcript.
3. Check that data moves only on the beats this lesson describes, and that backpressure holds the transfer.
4. Synthesize the RTL master, slave, or buffer with Yosys. Leave the UVM bench out of synthesis.

The lesson is done when the simulation matches AXI4 burst and size: AWLEN and AWSIZE address stepping. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.