Memory & FIFOs

IP blocks

• 16-Word 16-Bit Sync RAM with Byte Enable — L2 Upgrade Hardverilogsimsyn

  A 16-word by 16-bit synchronous RAM with independent write/read clocks and 2-bit byte enable support. Features active-low reset and registered read output for timing closure.

• 16×8 Sync RAM (No Reset, Registered Read) — L2 Upgrade Hardverilogsimsyn

  16-word by 8-bit synchronous RAM with independent write/read clocks and registered read output. No reset logic included.

• 32-Bit Asynchronous FIFO with Gray Pointer Encoding Hardsystemverilogsimsyn

  A configurable 32-bit asynchronous FIFO using AXI4-Stream interfaces and Gray code pointers for safe cross-clock-domain data transfer.

• 32-Bit Register with Byte Writes Easyverilogsimsyn

  A 32-bit register with independent byte-write enables for partial updates.

• 32x16 Synchronous Single-Port RAM Mediumverilogsimsyn

  32-word by 16-bit synchronous single-port RAM with combinational read.

• 4x8 1W1R Register File (Comb Read) Mediumverilogsimsyn

  A 4-deep by 8-bit wide register file with synchronous write and combinational read ports.

• 4×8 Sync RAM (Async Reset, Comb Read) Mediumverilogsimsyn

  Four-word 8-bit single-port RAM with async reset clear, synchronous write, and combinational read.

• 64-bit Wide Scratchpad RAM with Dual-Port Access Mediumverilogsimsyn

  256x64 dual-port RAM with byte-enable masking and combinational reads.

• 8-Bit Valid/Ready Skid Buffer Easyverilogsimsyn

  An 8-bit depth-1 skid buffer that absorbs backpressure by holding data until the consumer is ready. It asserts ready_in only when empty and maintains valid_out until valid_in deasserts.

• 8x16 Single-Port Sync RAM Mediumverilogsimsyn

  8x16 Single-Port Synchronous RAM with byte write enable. Depth: 8 words, Width: 16 bits. Read is synchronous (data available on next clock edge after address). Write is synchronous (data written on rising edge if we_n is low).

• 8x32 Dual-Read Register File Mediumverilogsimsyn

  An 8-deep, 32-bit wide register file with one synchronous write port and two independent combinational read ports.

• 8×8 Sync RAM (Async Reset, Comb Read, Loop Init) — L1 Upgrade Mediumverilogsimsyn

  8-bit wide, 8-depth synchronous single-port RAM with write-first read behavior and asynchronous reset.

• Asymmetric RAM WR8 RD16 — L2 Upgrade Mediumverilogsimsyn

  Asymmetric RAM with 8-bit write, 16-bit read, byte-enable, and invalidate-to-shadow functionality.

• Byte-Enable Regfile 8x32 — L2 Upgrade Mediumverilogsimsyn

  8x32 register file with byte-enable write support and shadow commit mechanism for atomic updates.

• CAM 4x8 with Invalidate Hardverilogsimsyn

  A 4-entry, 8-bit Content-Addressable Memory with individual entry invalidate capability.

• Circular Buffer 16x8 Mediumverilogsimsyn

  A synchronous circular buffer with 16 entries and 8-bit data width supporting push/pop operations with full/empty flags.

• Count-Based Sync FIFO with Dual Ready/Valid Hardsystemverilogsimsyn

  Single-clock FIFO that tracks occupancy with an explicit count register, exposes wready/rvalid on both producer and consumer sides, and defaults to depth 64 with 16-bit data.

• Credit-Based Ready Flow Control (4) Easyverilogsimsyn

  A credit-based flow control module that manages ready/valid handshakes with a maximum of 4 credits.

• Dual-Port RAM Write-First Bypass — L2 Upgrade Mediumverilogsimsyn

  Dual-Port RAM with write-first bypass on Port A and shadow buffer read with invalidation on Port B.

• Dual-Port Register File 4x16 — L2 Upgrade Hardverilogsimsyn

  Dual-Port Register File 4x16 with Invalidate, Shadow Commit, Byte Enable, and Hazard Detection for L2 upgrades.

• FWFT Sync FIFO 16x8 — L2 Upgrade Hardverilogsimsyn

  First-Word-Fall-Through synchronous FIFO with 16x8 depth and programmable almost-full/empty thresholds.

• FWFT Sync FIFO with Almost Full/Empty Hardverilogsimsyn

  A First-Word-Fall-Through (FWFT) synchronous FIFO module with configurable almost full and almost empty threshold flags for precise flow control.

• LIFO Stack 8-Bit Mediumverilogsimsyn

  Synchronous LIFO stack with depth 8, 8-bit data width, full/empty flags, and overflow/underflow protection.

• Ping-Pong Buffer 8x8 Mediumverilogsimsyn

  An 8x8 double-buffering module that swaps between two memory banks on a frame pulse for continuous data streaming.

• Pointer-Based Sync FIFO with Flush Hardverilogsimsyn

  Compact single-clock FIFO using extra-bit read/write pointers for full/empty detection, enable-style w_en/r_en ports, synchronous flush, and default depth 16 with 32-bit data.

• Regfile 1W2R 8x16 — L2 Upgrade Hardverilogsimsyn

  True dual-clock 1-write-2-read register file with 8x16 depth and registered read output.

• Regfile Shadow Buffer with Commit Mediumverilogsimsyn

  An 8x16 register file with shadow buffer support for speculative writes, atomic commit, and abort capabilities.

• Registered ROM 64x8 with Output Enable Mediumverilogsimsyn

  A registered Read-Only Memory with 64 words of 8 bits and an active-low output enable signal.

• ROM 16x8 Case Lookup Easyverilogsimsyn

  A combinational ROM with 16 words of 8 bits, mapping 4-bit addresses to their hex values.

• Simple CAM 4-Entry x 8-Bit — L2 Upgrade Hardverilogsimsyn

  Simple CAM 4-Entry x 8-Bit with search, write, and invalidate operations for L2 cache tag lookup.

• Stream Skid Buffer 2-Deep 8-bit Mediumverilogsimsyn

  A 2-deep skid buffer for 8-bit stream data that handles back-pressure and stalls.

• Synchronous 64-Bit FIFO with Full/Empty Flags Hardsystemverilogsimsyn

  A synchronous FIFO module with 64-bit data width, configurable depth, and status flags for full, empty, almost full, and almost empty conditions.

• Synchronous FIFO Depth Calculator (Counter-Based) Mediumverilogsimsyn

  A synchronous FIFO depth calculator using a counter-based approach to track buffer levels with configurable almost-full thresholds.

• True Dual-Port RAM 8x8 — L2 Upgrade Hardverilogsimsyn

  True dual-port RAM with independent write and read clock domains, 8 words x 8 bits, synchronous reset.

• Write-Priority Regfile 4x8 — L2 Upgrade Mediumverilogsimsyn

  4-word by 8-bit register file with write-priority, bit-masking, hold, and park controls.

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