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UVM Class | 0.1 Hello UVM: macros and uvm_info | RTLStudioWiki · UVM phases - 2
UVM Class | 0.2 Time master: UVM phase schedule | RTLStudioWiki · phase schedule - 3
UVM Class | 1.1 UVM sequence item and uvm_field macros | RTLStudioWiki · sequence item - 4
UVM Class | 1.2 UVM sequence and uvm_do in body() | RTLStudioWiki · sequence - 5
UVM Class | 1.3 Controlled randomness for FIFO traffic | RTLStudioWiki · FIFO constraints - 6
UVM Class | 1.4 UVM sequencer delivery path | RTLStudioWiki · sequencer - 7
UVM Class | 2.1 Driver: seq_item_port.get_next_item() | RTLStudioWiki · driver - 8
UVM Class | 2.2 Virtual interface via uvm_config_db | RTLStudioWiki · config_db - 9
UVM Class | 2.3 Handshake: item_done() and wave analysis | RTLStudioWiki · item_done - 10
UVM Class | 2.4 UVM monitor: sample FIFO pins | RTLStudioWiki · monitor - 11
UVM Class | 2.5 Analysis port: broadcast monitored data | RTLStudioWiki · analysis port - 12
UVM Class | 3.1 UVM agent: active vs passive is_active | RTLStudioWiki · agent - 13
UVM Class | 3.2 TLM analysis FIFO into the scoreboard | RTLStudioWiki · analysis FIFO - 14
UVM Class | 3.3 UVM scoreboard compare() and uvm_error | RTLStudioWiki · scoreboard - 15
UVM Class | 3.4 UVM env: verification environment pack | RTLStudioWiki · env - 16 Coming soon UVM Class | 3.5 UVM subscriber and covergroup on analysis port | RTLStudioWiki · covergroup
- 17 Coming soon UVM Class | 3.6 CDV: hit FIFO full and reach 100% coverage | RTLStudio
- 18 Coming soon UVM Class | 4.1 UVM test: orchestrate env and sequences | RTLStudio
- 19 Coming soon UVM Class | 4.2 raise_objection / drop_objection time control | RTLStudio
- 20 Coming soon UVM Class | 4.3 UVM factory: type_id::create() | RTLStudioWiki · factory
- 21 Coming soon UVM Class | 4.4 Factory override: swap in error-injection sequence | RTLStudioWiki · override
- 22 Coming soon UVM Class | 4.5 Configuration object for agent settings | RTLStudio
- 23 Coming soon UVM Class | 4.6 Virtual sequence: multi-agent fork-join conductor | RTLStudio
- 24 Coming soon UVM Class | 4.7 Pipelined driver: separate get() and put() (AXI prep) | RTLStudio
- 25 Coming soon UVM Class | 5.1 AMBA APB: PSEL, PENABLE, PWRITE timing | RTLStudio
- 26 Coming soon UVM Class | 5.2 Why UVM RAL maps registers to objects | RTLStudio
- 27 Coming soon UVM Class | 5.3 RAL adapter: reg ops to APB bus transactions | RTLStudio
- 28 Coming soon UVM Class | 5.4 Mission: reg_model frontdoor write() one-liner | RTLStudio
- 29 Coming soon UVM Class | 5.5 Mission: APB register field coverage 100% | RTLStudio
- 30 Coming soon UVM Class | 5.6 Next level: AXI masterclass invitation (AXI4-Lite demo) | RTLStudioWiki · AXI-Lite
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