RTL Studio Open IDE

Course order

Open a lesson page for the video · missing videos show Coming soon

  1. 1 0.1 HELLO RTLSTUDIO Verilog Class | 0.1 Hello RtlStudio | RTLStudioRTLStudio·Ready to play · Introduce RtlStudio simulation via $display and a wire-through DUT.
  2. 2 0.2 MY FIRST RTL Verilog Class | 0.2 My First RTL | RTLStudioRTLStudio·Ready to play · Write and verify a 2-input AND gate in Verilog using assign and &.Wiki · AND gate
  3. 3 1.1 WIRE VS REG Verilog Class | 1.1 wire vs reg | RTLStudioRTLStudio·Ready to playWiki · wire vs reg
  4. 4 1.2 UNDERSTANDING BUSES Verilog Class | 1.2 Understanding Buses | RTLStudioRTLStudio·Ready to play · Declare multi-bit buses and assign hexadecimal literals in Verilog.Wiki · buses
  5. 5 2.1 BASIC OPERATORS Verilog Class | 2.1 Basic operators | RTLStudioRTLStudio·Ready to playWiki · operators
  6. 6 2.2 CONCATENATION Verilog Class | 2.2 Concatenation | RTLStudioRTLStudio·Ready to play · Bundle signals with the concatenation operator to build wider buses.Wiki · concat
  7. 7 3.1 IF ELSE AND Verilog Class | 3.1 if-else and case | RTLStudioRTLStudio·Ready to playWiki · case mux
  8. 8 3.2 BLOCKING VS NON Verilog Class | 3.2 Blocking vs non-blocking | RTLStudioRTLStudio·Ready to playWiki · blocking vs NBA
  9. 9 4.1 INSTANTIATION Verilog Class | 4.1 Instantiation | RTLStudioRTLStudio·Ready to playWiki · modules
  10. 10 4.2 PARAMETER VS LOCALPARA Verilog Class | 4.2 parameter vs localparam | RTLStudioRTLStudio·Ready to playWiki · parameter
  11. 11 4.3 GENERATE STATEMENT Verilog Class | 4.3 generate statement | RTLStudioRTLStudio·Ready to playWiki · generate
  12. 12 4.4 FUNCTION VS TASK Verilog Class | 4.4 function vs task | RTLStudioRTLStudio·Ready to playWiki · function vs task
  13. 13 4.5 SYSTEM TASKS Verilog Class | 4.5 System tasks | RTLStudioRTLStudio·Ready to playWiki · system tasks
  14. 14 4.6 VERILOG HEADERS Verilog Class | 4.6 Verilog headers | RTLStudioRTLStudio·Ready to playWiki · headers
  15. 15 5.1 DELAY CONTROL Verilog Class | 5.1 Delay control | RTLStudioRTLStudio·Ready to playWiki · delay
  16. 16 5.2 CLOCK AND RESET Verilog Class | 5.2 Clock and reset | RTLStudioRTLStudio·Ready to playWiki · clock & reset
  17. 17 5.3 D FLIP FLOP Verilog Class | 5.3 D Flip-Flop | RTLStudioRTLStudio·Ready to playWiki · flip-flops
  18. 18 6.1 OVERFLOW Verilog Class | 6.1 Overflow | RTLStudioRTLStudio·Ready to playWiki · overflow
  19. 19 6.2 SIGNED VS UNSIGNED Verilog Class | 6.2 Signed vs unsigned | RTLStudioRTLStudio·Ready to playWiki · signed
  20. 20 7.1 BASIC COUNTER Verilog Class | 7.1 Basic counter | RTLStudioRTLStudio·Ready to playWiki · counter
  21. 21 7.2 ROLLOVER AND ENABLE Verilog Class | 7.2 Rollover and enable | RTLStudioRTLStudio·Ready to playWiki · enable / wrap
  22. 22 8.1 PIPELINE CONCEPT Verilog Class | 8.1 Pipeline concept | RTLStudioRTLStudio·Ready to playWiki · pipelines
  23. 23 8.2 PIPELINE VS NON Verilog Class | 8.2 Pipeline vs non-pipeline | RTLStudioRTLStudio·Ready to playWiki · throughput
  24. 24 8.3 DATA VALID SYNC Verilog Class | 8.3 Data Valid sync | RTLStudioRTLStudio·Ready to playWiki · valid
  25. 25 9.1 3 ALWAYS BLOCK Verilog Class | 9.1 3-always-block FSM | RTLStudioRTLStudio·Ready to play · Implement the state register update in a three-always-block FSM.Wiki · 3-process FSM
  26. 26 9.2 VENDING MACHINE BASIC Verilog Class | 9.2 Vending machine basic | RTLStudioRTLStudio·Ready to playWiki · vending FSM
  27. 27 9.3 VENDING MACHINE ADVANC Verilog Class | 9.3 Vending machine advanced | RTLStudioRTLStudio·Ready to playWiki · output logic
  28. 28 10.1 MEMORY INTERFACE BASIC Verilog Class | 10.1 Memory interface basics | RTLStudioRTLStudio·Ready to playWiki · memories
  29. 29 10.2 BRAM TIMING Verilog Class | 10.2 BRAM timing | RTLStudioRTLStudio·Ready to playWiki · BRAM latency
  30. 30 11.1 LOGIC AND SV Verilog Class | 11.1 logic and .sv | RTLStudioRTLStudio·Ready to playWiki · logic