Clock-Domain Crossing

IP blocks

• 1-Bit Handshake CDC Bridge Hardverilogsimsyn

  A robust 1-bit handshake protocol for crossing clock domains ensuring reliable data transfer without loss.

• 3-Stage Asynchronous Reset Synchronizer Easyverilogsimsyn

  Synchronizes an asynchronous active-low reset signal to a synchronous clock domain using a 3-stage flip-flop chain to minimize metastability.

• 4-Bit Bus Synchronizer (2-FF per bit) Easyverilogsimsyn

  A 4-bit bus synchronizer using a two-stage flip-flop per bit to safely transfer asynchronous signals into a synchronous domain.

• 4-Bit Gray Bus Synchronizer — L2 Upgrade Hardverilogsimsyn

  4-bit Gray code bus synchronizer with Valid/Ready handshake for asynchronous clock domain crossing.

• Async Handshake Pulse Bridge Hardverilogsimsyn

  Crosses a single-cycle pulse from src_clk to dst_clk using a req/ack toggle handshake.

• Async Set Sync-Clear Flag — L2 Upgrade Mediumverilogsimsyn

  Asynchronous set, synchronous clear flag with credit-based flow control for pulse transfer across clock domains.

• Asynchronous Reset Synchronizer for FIFO Gray Pointer Crossings Hardsystemverilogsimsyn

  2-stage asynchronous reset synchronizer chain for safe Gray-coded FIFO pointer synchronization across clock domains with active-low reset handling.

• Dual-Clock Pulse with Credit Return Hardverilogsimsyn

  Dual-clock domain crossing for single-cycle pulses with credit-based flow control.

• Enable Level Synchronizer — L1 Upgrade Mediumverilogsimsyn

  Enable Level Synchronizer with Busy Hold for CDC

• Four-Phase Req/Ack CDC Payload 16-bit Hardverilogsimsyn

  A 16-bit cross-domain clock synchronizer using a four-phase handshake protocol with backpressure support.

• Handshake CDC with 8-Bit Payload Hardverilogsimsyn

  Reliable asynchronous clock domain crossing using a two-way handshake protocol for 8-bit data payloads.

• Multi-Bit Bus Synchronizer (2-FF) Easyverilogsimsyn

  Synchronizes an 8-bit bus using a two-flop synchronizer chain per bit — educational follow-on to single-bit two_ff_sync.

• Multi-Bit Mux-Select Synchronizer — L2 Upgrade Hardverilogsimsyn

  Cross-clock domain synchronizer for multi-bit select signals using Gray code encoding to prevent metastability glitches.

• Pulse-Ack Round-Trip Across 2 Clocks Mediumverilogsimsyn

  Implements a pulse-acknowledgment round-trip mechanism across two asynchronous clock domains to ensure reliable single-cycle pulse transmission and acknowledgment.

• Req/Ack Payload Hold 8-bit Hardverilogsimsyn

  Asynchronous clock domain crossing module for 8-bit payloads using Req/Ack handshake with backpressure.

• Single-Cycle Pulse Synchronizer (2-FF + Edge Detector) Mediumsystemverilogsimsyn

  Transfers a single-clock-cycle pulse across asynchronous clock domains using a 2-FF synchronizer, edge detector, and pulse stretcher. Supports clock ratios up to 10:1 and variable reset polarity.

• Slow-Enable Fast Sample-Hold Easyverilogsimsyn

  Samples data on a rising edge of a synchronized slow enable signal in a fast clock domain.

• Toggle Bus Capture 4-bit Mediumverilogsimsyn

  Captures a 4-bit data bus synchronized to a destination clock domain using a toggle mechanism and 2-stage synchronizer.

• Toggle CDC with 8-bit Payload Hold Mediumverilogsimsyn

  Clock Domain Crossing module that transfers an 8-bit payload using a synchronized toggle signal for handshaking.

• Toggle Synchronizer 1-Bit — L2 Upgrade Hardverilogsimsyn

  Toggle synchronizer with 4-bit payload hold for asynchronous clock domain crossing.

• Toggle Synchronizer With Return Ack Hardverilogsimsyn

  Bidirectional toggle synchronizer with request and acknowledge paths for asynchronous clock domains.

• Two-Flip-Flop Synchronizer Chain — L1 Upgrade Mediumverilogsimsyn

  Two-flip-flop CDC synchronizer with async reset stretching for source and destination domains.

• Two-Stage Synchronizer Chain Mediumverilogsimsyn

  Parameterized two-stage synchronizer for single-bit asynchronous signal crossing with optional async reset support.

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