- 1 Coming soon RISC-V Core Class | 0.1 RV32I ISA and register ABI | RTLStudioWiki · RV32I fields
- 2 Coming soon RISC-V Core Class | 0.2 Load an instruction word and read it back | RTLStudio
- 3 Coming soon RISC-V Core Class | 1.1 Program counter with reset and PC+4 | RTLStudio
- 4 Coming soon RISC-V Core Class | 1.2 Instruction memory read port | RTLStudio
- 5 Coming soon RISC-V Core Class | 1.3 Opcode and funct field decode | RTLStudioWiki · decode
- 6 Coming soon RISC-V Core Class | 1.4 Immediate generator for all five formats | RTLStudio
- 7 Coming soon RISC-V Core Class | 1.5 Main control signal decoder | RTLStudio
- 8 Coming soon RISC-V Core Class | 1.6 Fetch and decode integration | RTLStudio
- 9 Coming soon RISC-V Core Class | 2.1 Register file with hardwired x0 | RTLStudio
- 10 Coming soon RISC-V Core Class | 2.2 ALU for R-type and I-type operations | RTLStudio
- 11 Coming soon RISC-V Core Class | 2.3 LUI and AUIPC upper immediate paths | RTLStudio
- 12 Coming soon RISC-V Core Class | 2.4 Branch condition compare unit | RTLStudio
- 13 Coming soon RISC-V Core Class | 2.5 JAL and JALR target calculation | RTLStudio
- 14 Coming soon RISC-V Core Class | 2.6 Execute datapath integration | RTLStudio
- 15 Coming soon RISC-V Core Class | 3.1 Load/store control and byte enables | RTLStudio
- 16 Coming soon RISC-V Core Class | 3.2 Load data sign and zero extension | RTLStudio
- 17 Coming soon RISC-V Core Class | 3.3 Store byte, half, and word alignment | RTLStudio
- 18 Coming soon RISC-V Core Class | 3.4 Address alignment check | RTLStudio
- 19 Coming soon RISC-V Core Class | 3.5 Local data memory with byte writes | RTLStudio
- 20 Coming soon RISC-V Core Class | 3.6 LSU and data memory integration | RTLStudio
- 21 Coming soon RISC-V Core Class | 4.1 Machine CSR file | RTLStudio
- 22 Coming soon RISC-V Core Class | 4.2 ECALL trap entry | RTLStudio
- 23 Coming soon RISC-V Core Class | 4.3 MRET and mepc restore | RTLStudio
- 24 Coming soon RISC-V Core Class | 4.4 mcause codes and the mtvec base | RTLStudio
- 25 Coming soon RISC-V Core Class | 4.5 External interrupt request port | RTLStudio
- 26 Coming soon RISC-V Core Class | 4.6 Trap and interrupt integration | RTLStudio
- 27 Coming soon RISC-V Core Class | 5.1 Stitch the single-cycle datapath | RTLStudio
- 28 Coming soon RISC-V Core Class | 5.2 The rv32i_core module interface | RTLStudio
- 29 Coming soon RISC-V Core Class | 5.3 Core testbench with a fibonacci loop | RTLStudio
- 30 Coming soon RISC-V Core Class | 5.4 Ultimate rv32i_core capstone | RTLStudio
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