Part 0 · RV Core Warming Up
RV32I ISA & register ABI
1 0.1 RV32I ISA AND Coming soon RISC-V Core Class | 0.1 RV32I ISA and register ABI | RTLStudioRTLStudio·Coming soon · daily upload
$readmemh and first ADD
2 0.2 LOAD AN INSTRUCTION Coming soon RISC-V Core Class | 0.2 Load an instruction word and read it back | RTLStudioRTLStudio·Coming soon · daily upload
Part 1 · Fetch & Decode
PC, reset, PC+4
3 1.1 PROGRAM COUNTER WITH Coming soon RISC-V Core Class | 1.1 Program counter with reset and PC+4 | RTLStudioRTLStudio·Coming soon · daily upload
Instruction memory port
4 1.2 INSTRUCTION MEMORY REA Coming soon RISC-V Core Class | 1.2 Instruction memory read port | RTLStudioRTLStudio·Coming soon · daily upload
Opcode / funct decode
5 1.3 OPCODE AND FUNCT Coming soon RISC-V Core Class | 1.3 Opcode and funct field decode | RTLStudioRTLStudio·Coming soon · daily upload
Immediate I/S/B/U/J
6 1.4 IMMEDIATE GENERATOR FO Coming soon RISC-V Core Class | 1.4 Immediate generator for all five formats | RTLStudioRTLStudio·Coming soon · daily upload
Main control decoder
7 1.5 MAIN CONTROL SIGNAL Coming soon RISC-V Core Class | 1.5 Main control signal decoder | RTLStudioRTLStudio·Coming soon · daily upload
Fetch-decode top
8 1.6 FETCH AND DECODE Coming soon RISC-V Core Class | 1.6 Fetch and decode integration | RTLStudioRTLStudio·Coming soon · daily upload
Part 2 · Execute Path
Register file x0..x31
9 2.1 REGISTER FILE WITH Coming soon RISC-V Core Class | 2.1 Register file with hardwired x0 | RTLStudioRTLStudio·Coming soon · daily upload · Build the 2-read / 1-write integer register file with x0 tied to zero.
ALU R-type & I-type
10 2.2 ALU FOR R Coming soon RISC-V Core Class | 2.2 ALU for R-type and I-type operations | RTLStudioRTLStudio·Coming soon · daily upload
LUI & AUIPC
11 2.3 LUI AND AUIPC Coming soon RISC-V Core Class | 2.3 LUI and AUIPC upper immediate paths | RTLStudioRTLStudio·Coming soon · daily upload
Branch compare unit
12 2.4 BRANCH CONDITION COMPA Coming soon RISC-V Core Class | 2.4 Branch condition compare unit | RTLStudioRTLStudio·Coming soon · daily upload
JAL & JALR target
13 2.5 JAL AND JALR Coming soon RISC-V Core Class | 2.5 JAL and JALR target calculation | RTLStudioRTLStudio·Coming soon · daily upload
Execute datapath top
14 2.6 EXECUTE DATAPATH INTEG Coming soon RISC-V Core Class | 2.6 Execute datapath integration | RTLStudioRTLStudio·Coming soon · daily upload
Part 3 · Load/Store & Local Memory
LSU control & byte_en
15 3.1 LOAD STORE CONTROL Coming soon RISC-V Core Class | 3.1 Load/store control and byte enables | RTLStudioRTLStudio·Coming soon · daily upload
Load + sign extension
16 3.2 LOAD DATA SIGN Coming soon RISC-V Core Class | 3.2 Load data sign and zero extension | RTLStudioRTLStudio·Coming soon · daily upload
Store SB/SH/SW
17 3.3 STORE BYTE HALF Coming soon RISC-V Core Class | 3.3 Store byte, half, and word alignment | RTLStudioRTLStudio·Coming soon · daily upload
Alignment & misalign flag
18 3.4 ADDRESS ALIGNMENT CHEC Coming soon RISC-V Core Class | 3.4 Address alignment check | RTLStudioRTLStudio·Coming soon · daily upload
Data memory (sync RAM)
19 3.5 LOCAL DATA MEMORY Coming soon RISC-V Core Class | 3.5 Local data memory with byte writes | RTLStudioRTLStudio·Coming soon · daily upload
LSU + DMEM top
20 3.6 LSU AND DATA Coming soon RISC-V Core Class | 3.6 LSU and data memory integration | RTLStudioRTLStudio·Coming soon · daily upload
Part 4 · CSR, Trap & IRQ Interface
CSR file (CSRRW/S/C)
21 4.1 MACHINE CSR FILE Coming soon RISC-V Core Class | 4.1 Machine CSR file | RTLStudioRTLStudio·Coming soon · daily upload
ECALL & trap entry
22 4.2 ECALL TRAP ENTRY Coming soon RISC-V Core Class | 4.2 ECALL trap entry | RTLStudioRTLStudio·Coming soon · daily upload
MRET & mepc restore
23 4.3 MRET AND MEPC Coming soon RISC-V Core Class | 4.3 MRET and mepc restore | RTLStudioRTLStudio·Coming soon · daily upload
mcause & mtvec modes
24 4.4 MCAUSE CODES AND Coming soon RISC-V Core Class | 4.4 mcause codes and the mtvec base | RTLStudioRTLStudio·Coming soon · daily upload
External IRQ input port
25 4.5 EXTERNAL INTERRUPT REQ Coming soon RISC-V Core Class | 4.5 External interrupt request port | RTLStudioRTLStudio·Coming soon · daily upload
Trap/IRQ integration top
26 4.6 TRAP AND INTERRUPT Coming soon RISC-V Core Class | 4.6 Trap and interrupt integration | RTLStudioRTLStudio·Coming soon · daily upload
Part 5 · Core Capstone
Stitch fetch-exec-LSU
27 5.1 STITCH THE SINGLE Coming soon RISC-V Core Class | 5.1 Stitch the single-cycle datapath | RTLStudioRTLStudio·Coming soon · daily upload
rv32i_core module shell
28 5.2 THE RV32I CORE Coming soon RISC-V Core Class | 5.2 The rv32i_core module interface | RTLStudioRTLStudio·Coming soon · daily upload
Core TB: fibonacci loop
29 5.3 CORE TESTBENCH WITH Coming soon RISC-V Core Class | 5.3 Core testbench with a fibonacci loop | RTLStudioRTLStudio·Coming soon · daily upload
Ultimate rv32i_core
30 5.4 ULTIMATE RV32I CORE Coming soon RISC-V Core Class | 5.4 Ultimate rv32i_core capstone | RTLStudioRTLStudio·Coming soon · daily upload