Bus Interfaces

IP blocks

• 2-Bit Read/Write Command Decode Easyverilogsimsyn

  Combinational module that decodes a 2-bit opcode into separate Read, Write, and Illegal status signals.

• 4-Slot Address Chip-Select Decoder Easyverilogsimsyn

  Combinational 2-bit to 4-slot one-hot chip-select decoder with global enable.

• 8-Bit Address Range Hit Easyverilogsimsyn

  Combinational module for 8-bit address range matching using base and mask inputs.

• 8-Bit Hold-on-Stall Register Mediumverilogsimsyn

  An 8-bit register that holds its output value when a stall signal is asserted and loads new data when the stall signal is deasserted.

• 8-Bit Valid/Ready Register Slice Mediumverilogsimsyn

  A single-cycle valid/ready register slice for 8-bit data paths with backpressure handling.

• 8-Bit Write Merge with Byte Mask Easyverilogsimsyn

  Combinational logic for merging 8-bit data using a byte mask.

• AHB-Lite Simple Master Hardsystemverilogsimsyn

  A simple AHB-Lite master controller for SystemVerilog designs supporting single-cycle transactions.

• AHB-Lite Single-Beat Master Hardsystemverilogsimsyn

  Minimal AHB-Lite master that issues one read or write transfer per request.

• AHB-Lite Slave Interface Hardsystemverilogsimsyn

  Single-beat AHB-Lite slave with configurable address range, combinational read response, and write capture on full-word granularity.

• APB3 Master (Single-Transaction Pipeline) Hardsystemverilogsimsyn

  APB3 master with setup/access phases and one outstanding transaction.

• APB3 Master with Burst Support and Backpressure Handling Hardsystemverilogsimsyn

  A fully compliant APB3 master controller supporting single and burst transactions with auto-increment and backpressure handling.

• APB3 Slave Register Interface Hardsystemverilogsimsyn

  Configurable APB3 slave with word-aligned register file, byte-lane writes, and zero-wait-state PREADY.

• AXI-Lite 4-Register Bank Hardsystemverilogsimsyn

  A SystemVerilog IP core implementing a slave AXI-Lite interface with a 4-register bank and byte strobe support.

• AXI-Lite Read-Only Slave 4 Regs Hardverilogsimsyn

  AXI4-Lite slave with 4 read-only registers and ignored write channels.

• AXI-Lite Write-Only Slave 4 Regs Hardverilogsimsyn

  AXI4-Lite compliant write-only slave with 4 registers and byte enable support. Read accesses return DECERR.

• AXI-Stream 1-to-2 Demux Hardverilogsimsyn

  AXI-Stream 1-to-2 Demux routing TDATA/TKEEP/TLAST based on TDEST[0]

• AXI-Stream Broadcast 1-to-2 Hardverilogsimsyn

  AXI-Stream Broadcast 1-to-2 with AND-ready policy

• AXI-Stream Mux 2-to-1 with TLAST Priority Hardverilogsimsyn

  AXI-Stream 2-to-1 multiplexer with priority arbitration and TLAST preservation.

• AXI-Stream Register Slice — L2 Upgrade Hardverilogsimsyn

  AXI-Stream Register Slice with Retry/Timeout/Error Decode

• AXI-Stream Skid Buffer Hardverilogsimsyn

  Single-entry skid buffer for AXI-Stream interfaces to handle backpressure.

• AXI-Stream SOF Counter with Skid Hardverilogsimsyn

  Counts Start-of-Frame beats in an AXI-Stream interface with skid buffer support.

• AXI4-Lite Simple Master (Single Beat) Hardsystemverilogsimsyn

  AXI4-Lite Simple Master (Single Beat)

• AXI4-Lite Simple Slave Hardverilogsimsyn

  A basic AXI4-Lite slave module implementing a 4x32-bit register file with standard handshake protocols.

• Valid Hold Until Ack Mediumverilogsimsyn

  Registers valid signal and data until acknowledgment is received.

• Wishbone B3 Single-Beat Master Hardsystemverilogsimsyn

  Wishbone B3 master for classic single-beat read/write transactions.

• Wishbone B3 Slave (32-Bit, Single-Cycle) Hardsystemverilogsimsyn

  32-bit Wishbone B3 slave with combinational ack and a small register file.

• Wishbone B3 Slave (4 × 32-Bit Registers) — L2 Upgrade Hardverilogsimsyn

  Wishbone B3 Slave with 4x32-bit registers and wait cycle timeout detection.

• Wishbone B3 to AHB-Lite Simple Bridge Hardverilogsimsyn

  Converts Wishbone B3 master transactions into AHB-Lite master transactions for single-word transfers.

• Wishbone Byte-Strobe Slave 8 Hardverilogsimsyn

  A Wishbone B.4 compliant slave module with byte-strobe support and a 256-byte internal memory map.

• Wishbone Classic Slave with RTY Hardverilogsimsyn

  A Wishbone Classic slave module that supports the Retry (RTY) response mechanism for handling busy states during read and write transactions.

• Wishbone Classic to Pipelined Bridge Hardverilogsimsyn

  Converts Wishbone Classic slave interface to Wishbone Pipelined master interface for protocol bridging.

• Wishbone Simple Master — L2 Upgrade Hardverilogsimsyn

  Wishbone Simple Master with configurable retry and timeout logic for handling slave stalls and errors.

• Wishbone Slave 4-Register File — L2 Upgrade Hardverilogsimsyn

  Wishbone slave with 4 registers, retry for invalid addresses, and timeout detection to prevent bus deadlocks.

• Wishbone to Simple CSR Bridge Hardverilogsimsyn

  Single-cycle Wishbone B3 slave bridging to a configurable array of 32-bit CSRs with byte-select write support.

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