A practical reference for RTL coding theory: how digital hardware maps to clean, synthesizable Verilog / SystemVerilog.
This wiki is the short theory book. Learn is the video + lab track. Open a topic when you need the pattern; use Learn when you want a timed walkthrough.
How to use a page:
- Skim the definition and the diagram
- Copy the coding pattern (and the wrong vs right pair)
- Follow Related into a Learn lesson or an IDE example
Use the sidebar (or the section cards below) to browse. Pair this wiki with:
- Learn — structured lecture tracks with videos
- Guides — how to simulate and synthesize inside RTL Studio
- Open IDE — try the patterns yourself
Content stays short and reusable — theory first, then coding habits that synthesis and verification tools like.