- 1 Coming soon AXI Class | 0.1 AXI Protocol Overview: VALID/READY handshake | RTLStudioWiki · valid/ready
- 2 Coming soon AXI Class | 0.2 AXI SV interface and modport: master and slave directions | RTLStudio
- 3 Coming soon AXI Class | 1.1 Write channels (AW, W, B) RTL: AWREADY and WREADY handshake | RTLStudio
- 4 Coming soon AXI Class | 1.2 Read channels (AR, R) RTL: ARREADY and RVALID handshake | RTLStudio
- 5 Coming soon AXI Class | 1.3 SV struct register map: packed CTRL, STAT, and DATA | RTLStudio
- 6 Coming soon AXI Class | 1.4 AXI4-Lite slave FSM: enum states and case transitions | RTLStudio
- 7 Coming soon AXI Class | 1.5 Skid buffer: decouple VALID/READY timing on an AXI channel | RTLStudio
- 8 Coming soon AXI Class | 2.1 AXI sequence item: address, data, and UVM field macros | RTLStudio
- 9 Coming soon AXI Class | 2.2 AXI driver: VALID/READY handshake and item_done | RTLStudio
- 10 Coming soon AXI Class | 2.3 AXI monitor and scoreboard: sample bus and compare registers | RTLStudio
- 11 Coming soon AXI Class | 2.4 UVM RAL adapter for AXI: reg2bus and bus2reg | RTLStudio
- 12 Coming soon AXI Class | 2.5 Coverage-driven AXI verification: 100% READY backpressure mission | RTLStudio
- 13 Coming soon AXI Class | 3.1 AXI4 burst and size: AWLEN and AWSIZE address stepping | RTLStudio
- 14 Coming soon AXI Class | 3.2 Write data channel: WSTRB and WLAST for write bursts | RTLStudio
- 15 Coming soon AXI Class | 3.3 Read data channel: RLAST on the final read beat | RTLStudio
- 16 Coming soon AXI Class | 3.4 Outstanding transactions: AWID tracking FIFO | RTLStudio
- 17 Coming soon AXI Class | 3.5 Out-of-order and interleaving: observe-only routing theory | RTLStudio
- 18 Coming soon AXI Class | 3.6 AXI4 slave memory controller: BRAM wrapper bridge | RTLStudio
- 19 Coming soon AXI Class | 4.1 Dynamic array payload: runtime-sized burst data in the sequence item | RTLStudio
- 20 Coming soon AXI Class | 4.2 Independent channel driver: fork/join_none on five AXI channels | RTLStudio
- 21 Coming soon AXI Class | 4.3 ID tracking monitor: associative array for outstanding transactions | RTLStudio
- 22 Coming soon AXI Class | 4.4 Out-of-order scoreboard: match responses by BID and RID | RTLStudio
- 23 Coming soon AXI Class | 4.5 AXI virtual sequence: parallel read and write traffic | RTLStudio
- 24 Coming soon AXI Class | 5.1 SVA basics for AXI: stable data while VALID waits for READY | RTLStudio
- 25 Coming soon AXI Class | 5.2 SVA burst and ID checker: AWLEN versus WLAST beat count | RTLStudio
- 26 Coming soon AXI Class | 5.3 AXI crossbar interconnect: observe-only routing theory | RTLStudio
- 27 Coming soon AXI Class | 5.4 Multi-master arbiter RTL: round-robin grant logic | RTLStudio
- 28 Coming soon AXI Class | 5.5 AXI error handling: SLVERR and DECERR in UVM sequences | RTLStudio
- 29 Coming soon AXI Class | 5.6 AXI exclusive access: ARLOCK and EXOKAY response handling | RTLStudio
- 30 Coming soon AXI Class | 5.7 The ultimate AXI system: 2x2 capstone with UVM, SVA, and 100% coverage | RTLStudio
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