Clock Generators

IP blocks

• 1-Cycle Data Delay Easyverilogsimsyn

  A registered delay element that holds input data for one clock cycle with asynchronous reset and synchronous enable.

• 16-Bit DDS Phase Accumulator — L2 Upgrade Mediumverilogsimsyn

  16-bit DDS phase accumulator with dual phase output, freeze, and stretch control.

• 2:1 Clock Divider (Toggle Flip-Flop) Easyverilogsimsyn

  A simple toggle flip-flop that divides the input clock frequency by two.

• 4-Phase Clock-Enable Sequencer — L1 Upgrade — L2 Upgrade Mediumverilogsimsyn

  Glitch-free 4-phase clock-enable sequencer with configurable M/N division counters.

• Burst Enable for N Cycles — L1 Upgrade — L2 Upgrade Mediumverilogsimsyn

  Latch-free, fully synthesizable clock divider with burst, freeze, and clear capabilities. Uses m, n, and div inputs in the comparison logic to ensure no unused ports.

• CE Pulse Every N Cycles Mediumverilogsimsyn

  Generates a single-cycle clock enable pulse every N clock cycles when enabled.

• Clock Enable with Soft-Reset Stretch — L2 Upgrade Mediumverilogsimsyn

  Configurable clock enable generator with stretch and phase offset capabilities for precise timing control.

• Clock-Enable Divider (CE Pulse) — L1 Upgrade — L2 Upgrade Easyverilogsimsyn

  Glitch-free clock enable divider with M/N inputs. Generates a pulse on ce_out when counter reaches M-1. Counter resets when reaching N-1. M must be <= N.

• Clock-Enable Stretcher N — L1 Upgrade — L2 Upgrade Mediumverilogsimsyn

  Configurable clock-enable stretcher with busy-handshaking support and m/n ratio control.

• Divide-by-3 Clock (50% Duty) Mediumverilogsimsyn

  A divide-by-3 clock generator that produces a 50% duty cycle output using a 2-bit state machine.

• Dual-Edge DDR Sampler — L2 Upgrade Mediumverilogsimsyn

  Dual-edge DDR sampler with configurable clock division and enable control.

• Duty-Correct Divide-by-2 — L1 Upgrade — L2 Upgrade Mediumverilogsimsyn

  Duty-correct divide-by-N using M/N ratio with enable and registered output.

• Fractional Clock Divider with Jitter Control Mediumsystemverilogsimsyn

  Synthesizable fractional clock divider using phase accumulation for low jitter.

• Fractional Clock Enable M/N — L2 Upgrade Mediumverilogsimsyn

  Fractional Clock Enable M/N with Used-MN Indicator using Bresenham accumulator.

• Glitch-Free Clock Select 2 — L2 Upgrade Hardverilogsimsyn

  Glitch-free clock selector with busy indicator for two asynchronous clock sources.

• Integer Clock Divider Easyverilogsimsyn

  Parameterized integer clock divider with 50% duty cycle supporting even divisors from 2 to 255.

• Lost-Clock Detector — L2 Upgrade Mediumverilogsimsyn

  Dual-phase lost-clock detector with configurable threshold and count enable.

• Parameterized Clock Enable Generator — L2 Upgrade Mediumverilogsimsyn

  A parameterized clock enable generator that produces a periodic enable pulse based on M/N division parameters, with global reset and enable control.

• Pulse-to-Toggle Clock Maker — L1 Upgrade — L2 Upgrade Mediumverilogsimsyn

  Converts an asynchronous pulse into a glitch-free toggled clock output with configurable duty cycle and enable control.

• Run Window for N Cycles Mediumverilogsimsyn

  Generates a busy signal for a configurable number of clock cycles triggered by a start pulse.

• Startup Ready After N Cycles Mediumverilogsimsyn

  Asserts a ready signal after a configurable number of clock cycles following reset.

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