Part 0 · SV Warming Up Hello SystemVerilog 1
0.1
LOGIC AND DESIGN
SystemVerilog Class | 0.1 logic and design.sv | RTLStudio RTLStudio · Ready to play 2
0.2
GOODBYE WIRE REG
SystemVerilog Class | 0.2 Goodbye wire/reg, Hello logic | RTLStudio RTLStudio · Ready to play Part 1 · Design in SV Aggregate Data Types 3
1.1
TYPEDEF AND ENUM
SystemVerilog Class | 1.1 typedef and enum | RTLStudio RTLStudio · Ready to play 4
1.2
PACKED VS UNPACKED
SystemVerilog Class | 1.2 Packed vs Unpacked arrays | RTLStudio RTLStudio · Ready to play 5
1.3
STRUCT STRUCTURES
SystemVerilog Class | 1.3 struct (Structures) | RTLStudio RTLStudio · Ready to play 6
1.4
STRING AND SFORMATF
SystemVerilog Class | 1.4 string and $sformatf | RTLStudio RTLStudio · Ready to play Processes 7
1.5
ALWAYS COMB
SystemVerilog Class | 1.5 always_comb | RTLStudio RTLStudio · Ready to play 8
1.6
ALWAYS FF
SystemVerilog Class | 1.6 always_ff | RTLStudio RTLStudio · Ready to play Interfaces 9
1.7
INTERFACE BASICS
SystemVerilog Class | 1.7 interface basics | RTLStudio RTLStudio · Ready to play 10
1.8
MODPORTS
SystemVerilog Class | 1.8 modports | RTLStudio RTLStudio · Ready to play Packages 11
1.9
PACKAGE AND IMPORT
SystemVerilog Class | 1.9 package and import | RTLStudio RTLStudio · Ready to play Part 2 · Verification & OOP Dynamic Data Types 12
2.1
DYNAMIC ARRAYS
SystemVerilog Class | 2.1 Dynamic Arrays | RTLStudio RTLStudio · Ready to play · Allocate dynamic arrays at runtime with new[] in testbench code. 13
2.2
QUEUES
SystemVerilog Class | 2.2 Queues | RTLStudio RTLStudio · Ready to play 14
2.3
ASSOCIATIVE ARRAYS
SystemVerilog Class | 2.3 Associative Arrays | RTLStudio RTLStudio · Ready to play Classes & OOP Basics 15
2.4
CLASS AND HANDLE
SystemVerilog Class | 2.4 Class and Handle | RTLStudio RTLStudio · Ready to play 16
2.5
LOCAL AND STATIC
SystemVerilog Class | 2.5 local and static members | RTLStudio RTLStudio · Ready to play 17
2.6
VIRTUAL INTERFACE
SystemVerilog Class | 2.6 virtual interface | RTLStudio RTLStudio · Ready to play Advanced OOP 18
2.7
INHERITANCE EXTENDS
Coming soon
SystemVerilog Class | 2.7 Inheritance (extends) | RTLStudio RTLStudio · Coming soon · daily upload
19
2.8
VIRTUAL METHODS
Coming soon
SystemVerilog Class | 2.8 virtual methods | RTLStudio RTLStudio · Coming soon · daily upload
Part 3 · Advanced SV & Mini-UVM Downcasting with $cast 20
3.1
DOWNCASTING WITH CAST
Coming soon
SystemVerilog Class | 3.1 Downcasting with $cast (UVM Key 2) | RTLStudio RTLStudio · Coming soon · daily upload · Safely downcast class handles with $cast for UVM-style verification.
Timing & Synchronization 21
3.2
CLOCKING BLOCK
Coming soon
SystemVerilog Class | 3.2 clocking block | RTLStudio RTLStudio · Coming soon · daily upload
22
3.3
MAILBOX
Coming soon
SystemVerilog Class | 3.3 mailbox | RTLStudio RTLStudio · Coming soon · daily upload
23
3.4
SEMAPHORE
Coming soon
SystemVerilog Class | 3.4 semaphore | RTLStudio RTLStudio · Coming soon · daily upload
Constraint Random Verification 24
3.5
CONSTRAINT RANDOM RAND
Coming soon
SystemVerilog Class | 3.5 Constraint Random (rand/randomize) | RTLStudio RTLStudio · Coming soon · daily upload
25
3.6
CONSTRAINT BLOCKS
Coming soon
SystemVerilog Class | 3.6 constraint blocks | RTLStudio RTLStudio · Coming soon · daily upload
26
3.7
FUNCTIONAL COVERAGE MA
Coming soon
SystemVerilog Class | 3.7 functional coverage (manual bins, Verilator) | RTLStudio RTLStudio · Coming soon · daily upload
Assertions 27
3.8
IMMEDIATE ASSERTIONS
Coming soon
SystemVerilog Class | 3.8 Immediate Assertions | RTLStudio RTLStudio · Coming soon · daily upload
28
3.9
CONCURRENT ASSERTIONS
Coming soon
SystemVerilog Class | 3.9 Concurrent Assertions (SVA) | RTLStudio RTLStudio · Coming soon · daily upload
Mini-UVM 29
3.10
MINI UVM ARCHITECTURE
Coming soon
SystemVerilog Class | 3.10 Mini-UVM: Architecture (Theory) | RTLStudio RTLStudio · Coming soon · daily upload
30
3.11
MINI UVM FULL
Coming soon
SystemVerilog Class | 3.11 Mini-UVM: Full Integration (Capstone) | RTLStudio RTLStudio · Coming soon · daily upload
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