Interface Protocols

IP blocks

• 1-Bit GPIO Pin Driver (Combinational) — L1 Upgrade — L2 Upgrade Mediumverilogsimsyn

  A 1-bit GPIO pin driver that detects edge transitions and generates a sticky interrupt flag.

• 32-Bit MMIO GPIO (DI Read, Byte-Strobed DO) — L2 Upgrade Mediumverilogsimsyn

  32-Bit MMIO GPIO with byte-strobed data output and sticky pin-change interrupt.

• 8-Bit GPIO Output Register Mediumverilogsimsyn

  8-Bit GPIO Output Register with synchronous load and active-low reset

• 8-Bit GPIO Set/Clear Register Mediumverilogsimsyn

  An 8-bit GPIO register with atomic Set and Clear operations where Clear takes priority over Set.

• 8-Bit GPIO with Direction and Rising-Edge IRQ Mediumverilogsimsyn

  Register-mapped 8-bit GPIO with per-pin direction, data registers, and rising-edge interrupt generation.

• I2C Arbitration Lost Detector Mediumverilogsimsyn

  Detects I2C arbitration loss by comparing driven and sampled SDA values. Outputs a sticky flag until cleared.

• I2C Bus Idle Timeout Mediumverilogsimsyn

  Detects I2C bus idle conditions based on SCL and SDA levels with configurable threshold.

• I2C Clock Stretch Detector Hardverilogsimsyn

  Detects I2C clock stretching by counting SCL low cycles against a configurable threshold.

• I2C NACK Sticky Flag Detector Mediumverilogsimsyn

  Detects I2C NACK conditions during the ACK phase and latches a sticky flag until reset.

• I2C Start/Stop Detector Mediumverilogsimsyn

  Detects I2C Start and Stop conditions synchronously on the SCL rising edge.

• JTAG TAP Controller Hardverilogsimsyn

  Synthesizable IEEE 1149.1 JTAG TAP Controller with 32-bit DR and IR paths.

• Lightweight I²C Master Controller (Standard Mode) Hardverilogsimsyn

  A lightweight I²C master controller supporting Standard Mode (100 kHz) with configurable clock parameters and basic transaction control.

• Lightweight I²C Slave Controller (Standard Mode) Hardsystemverilogsimsyn

  A lightweight I²C slave controller that translates I²C read/write operations into simple register file transfers with clock stretching support.

• SPI Master Lite Hardverilogsimsyn

  Minimal SPI master for CPOL=0, CPHA=0, 8-bit transfers with start/done handshake.

• SPI Mode-0 Host (8-Bit Frames) Hardverilogsimsyn

  SPI host/controller operating in CPOL=0 CPHA=0 with 8-bit shift frames.

• SPI Mode-3 Slave (CPOL=1, CPHA=1) 8-Bit Hardverilogsimsyn

  SPI Mode-3 Slave (CPOL=1, CPHA=1) 8-Bit

• SPI Slave Controller (Mode 0) Hardsystemverilogsimsyn

  Synthesizable SPI slave with ready/valid byte interface, LSB-first Mode 0 shifting, and chip-select framed transfers.

• Sticky Button Set/Clear Flag Mediumverilogsimsyn

  A registered sticky flag module with set and clear inputs where clear takes priority.

• Synthesizable SystemVerilog UART Core (8-N-1) Hardsystemverilogsimsyn

  A synthesizable 8-N-1 UART with valid/ready TX/RX handshakes and parameterizable baud timing.

• UART with Integrated TX/RX FIFOs Hardsystemverilogsimsyn

  8N1 UART Core with Configurable Depth TX and RX FIFOs. Supports backpressure and interrupt-ready status flags.

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