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Lectures

Seven masterclass tracks. Open a course page for in-page lecture videos — new uploads land daily on YouTube until the set is complete.

• FREE 30 Lessons VERILOG CLASS RTLStudio

  Verilog Class | RTLStudio

  Free

  30 lessons · 4 parts · 30 videos ready

  Write Verilog RTL in the browser, run simulation, read VCD waveforms, and review Yosys synthesis — no desktop EDA install.

  **30 lessons** · about 5 minutes each · roughly 3 hours total

  Full outline (30 lessons)

  Part 0 · Warming Up

  Get comfortable with RtlStudio before diving into syntax.

  1. 0.1 · Hello RtlStudio — Introduce RtlStudio simulation via $display and a wire-through DUT.
  2. 0.2 · My First RTL — Write and verify a 2-input AND gate in Verilog using assign and &.

  Part 1 · Verilog Core Syntax

  Language mechanics first — confirm behavior on waveforms, not big designs yet.

  Data Types

  1. 1.1 · wire vs reg — Declare ports as wire or reg based on assignment style in combinational vs sequential logic.
  2. 1.2 · Understanding Buses — Declare multi-bit buses and assign hexadecimal literals in Verilog.

  Combinational Logic

  1. 2.1 · Basic operators — Basic Verilog operators (+, &, |) using continuous assignments in combinational logic.
  2. 2.2 · Concatenation — Bundle signals with the concatenation operator to build wider buses.

  Sequential Logic

  1. 3.1 · if-else and case — Implement a 4-to-1 multiplexer using case statements and verify all select branches.
  2. 3.2 · Blocking vs non-blocking — Use non-blocking assignments in clocked always blocks to model flip-flops correctly.

  Hierarchy & Advanced

  1. 4.1 · Instantiation — Instantiate sub-modules using named port mapping and connect them in a testbench.
  2. 4.2 · parameter vs localparam — Use parameter (externally overridable) vs localparam (fixed internal constant) in modules.
  3. 4.3 · generate statement — Use generate-for loops to automate hardware instantiation for scalable RTL.
  4. 4.4 · function vs task — When to use functions (combinational, no timing) vs tasks (simulation timing, delays).
  5. 4.5 · System tasks — Use $readmemb to initialize memory arrays from text files in testbenches.
  6. 4.6 · Verilog headers — Verilog header files (.vh) with ` include ` and define `` macros for global constants.

  Part 2 · Practical Hardware Design

  Apply syntax to the blocks non-memory RTL engineers build in practice.

  Testbench & Base Logic

  1. 5.1 · Delay control — Use delay controls (#N) in testbenches to sequence stimulus at precise simulation times.
  2. 5.2 · Clock and reset — Generate a continuous clock and properly deassert asynchronous reset to initialize a clocked register.
  3. 5.3 · D Flip-Flop — Complete the sensitivity list for a D flip-flop with asynchronous reset to prevent latch inference.

  Data Handling

  1. 6.1 · Overflow — Detect overflow in an N-bit counter by comparing count to its maximum value.
  2. 6.2 · Signed vs unsigned — Use $signed() casting for correct signed arithmetic and avoid misinterpretation of bit patterns.

  Counter

  1. 7.1 · Basic counter — Build and verify an 8-bit synchronous up-counter with a minimal testbench.
  2. 7.2 · Rollover and enable — Implement a counter that increments only when enabled and resets at a custom maximum value.

  Pipeline

  1. 8.1 · Pipeline concept — Implement a 2-stage pipeline to compute (A + B) * C across register stages.
  2. 8.2 · Pipeline vs non-pipeline — Compare latency and throughput of pipelined vs non-pipelined multiplier implementations.
  3. 8.3 · Data Valid sync — Synchronize the valid control signal through a multi-stage pipeline alongside data.

  FSM (Finite State Machine)

  1. 9.1 · 3-always-block FSM — Implement the state register update in a three-always-block FSM.
  2. 9.2 · Vending machine basic — Implement next-state logic for a 4-state vending machine FSM from coin inputs.
  3. 9.3 · Vending machine advanced — Implement output logic for a vending machine FSM to drive dispense and change in the COIN3 state.

  Memory Interface

  1. 10.1 · Memory interface basics — Implement synchronous memory write logic and verify read-after-write for a 16×8-bit array.
  2. 10.2 · BRAM timing — Synchronous BRAM 1-cycle read latency; register the read address in the DUT.

  Part 3 · Next Frontier

  The Bridge to SV

  1. 11.1 · logic and .sv — Transition from Verilog to SystemVerilog by replacing wire/reg with unified logic in a memory-based DUT.

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• PRO 30 Lessons SYSTEMVERILOG CLASS RTLStudio

  SystemVerilog Class | RTLStudio

  Pro

  30 lessons · 4 parts · 30 videos ready

  Pro track for modern SystemVerilog design and verification — logic, interfaces, packages, OOP, constrained-random, coverage, SVA, and Mini-UVM.

  **30 lessons** · about 5 minutes each · roughly 3 hours total

  Full outline (30 lessons)

  Part 0 · SV Warming Up

  Move from Verilog to SystemVerilog and get the Verilator simulation flow running.

  Hello SystemVerilog

  1. 0.1 · logic and design.sv — Introduce the unified logic type in SystemVerilog to replace legacy wire/reg in simple combinational logic.
  2. 0.2 · Goodbye wire/reg, Hello logic — Replace legacy wire/reg with logic in module ports and internal signals to unify net/variable semantics.

  Part 1 · Design in SV

  Synthesizable SystemVerilog that removes Verilog ambiguity and cuts boilerplate.

  Aggregate Data Types

  1. 1.1 · typedef and enum — Declare and use typedef enums for FSM state names instead of raw integers.
  2. 1.2 · Packed vs Unpacked arrays — See how packed and unpacked arrays differ in syntax, memory layout, and slicing behavior.
  3. 1.3 · struct (Structures) — Define packed structs to group control and payload fields into a single packet type.
  4. 1.4 · string and $sformatf — Use string variables and $sformatf for formatted simulation logging in testbenches.

  Processes

  1. 1.5 · always_comb — Use always_comb blocks for safe, explicit combinational logic — no sensitivity list required.
  2. 1.6 · always_ff — Model clocked sequential registers with always_ff, asynchronous reset, and non-blocking assignments.

  Interfaces

  1. 1.7 · interface basics — Bundle shared signals into an interface to simplify DUT wiring and improve modularity.
  2. 1.8 · modports — Use modports to define and enforce input/output directions for master and slave endpoints.

  Packages

  1. 1.9 · package and import — Define and import packages to centralize shared types and constants across design and testbench.

  Part 2 · Verification & OOP

  Software-side verification: dynamic data structures, classes, and the first UVM master keys.

  Dynamic Data Types

  1. 2.1 · Dynamic Arrays — Allocate dynamic arrays at runtime with new[] in testbench code.
  2. 2.2 · Queues — Use push_back() and pop_front() to manage dynamic data buffers with queues.
  3. 2.3 · Associative Arrays — Declare associative arrays with correct index types for sparse memory modeling.

  Classes & OOP Basics

  1. 2.4 · Class and Handle — Define classes and instantiate handles for object-oriented verification.
  2. 2.5 · local and static members — Use static and local members to share state and hide internal class data.
  3. 2.6 · virtual interface — Connect verification classes to hardware instances using virtual interfaces.

  Advanced OOP

  1. 2.7 · Inheritance (extends) — Use extends to inherit and extend class definitions for verification reuse.
  2. 2.8 · virtual methods — Enable polymorphism with virtual methods so child classes can override behavior.

  Part 3 · Advanced SV & Mini-UVM

  Timing, concurrency, constrained-random verification, assertions, and a pure-SV Mini-UVM environment.

  Downcasting with $cast

  1. 3.1 · Downcasting with $cast (UVM Key 2) — Safely downcast class handles with $cast for UVM-style verification.

  Timing & Synchronization

  1. 3.2 · clocking block — Define a clocking block to synchronize stimulus with the DUT clock and avoid race conditions.
  2. 3.3 · mailbox — Pass transactions between generator and driver threads with mailbox put/get.
  3. 3.4 · semaphore — Use semaphores so parallel threads acquire shared resources without collision.

  Constraint Random Verification

  1. 3.5 · Constraint Random (rand/randomize) — Generate unpredictable stimulus with rand and randomize() to hit corner-case bugs.
  2. 3.6 · constraint blocks — Limit random value generation to valid protocol ranges with constraint blocks.
  3. 3.7 · functional coverage (manual bins, Verilator) — Implement manual functional coverage with explicit bin comparisons in a Verilator-safe testbench.

  Assertions

  1. 3.8 · Immediate Assertions — Use immediate assertions in testbenches to catch bugs exactly when they happen.
  2. 3.9 · Concurrent Assertions (SVA) — Define and verify a next-cycle request–acknowledge protocol with concurrent assertions.

  Mini-UVM

  1. 3.10 · Mini-UVM: Architecture (Theory) — Introduce the UVM component hierarchy through a minimal, observe-only testbench.
  2. 3.11 · Mini-UVM: Full Integration (Capstone) — Wire the virtual interface and mailbox inside the environment class to complete a Mini-UVM skeleton.

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• PRO 30 Lessons UVM CLASS RTLStudio

  UVM Class | RTLStudio

  Pro

  30 lessons · 6 parts · 15 videos ready

  Pro UVM verification track — FIFO CDV missions, agents, scoreboards, factory overrides, virtual sequences, APB, and UVM RAL.

  **30 lessons** · about 5 minutes each · roughly 3 hours total

  Full outline (30 lessons)

  Part 0 · UVM Warming Up

  How SystemVerilog classes evolve into the UVM verification framework.

  Hello UVM

  1. 0.1 · Hello UVM: macros and uvm_info — Introduce UVM logging with uvm_info in a console-first testbench without UVM components.
  2. 0.2 · Time master: UVM phase schedule — Implement build, connect, run, and report phases in a test class and observe execution order.

  Part 1 · Stimulus Generation

  Create randomized transactions and deliver them safely to the DUT.

  Sequence Item

  1. 1.1 · UVM sequence item and uvm_field macros — Define a FIFO sequence item and register fields with uvm_field macros for copy, compare, and print.

  Sequence

  1. 1.2 · UVM sequence and uvm_do in body() — Generate FIFO write transactions with a UVM sequence using uvm_do in body().

  Constraints

  1. 1.3 · Controlled randomness for FIFO traffic — Constrain sequence items to produce valid mixed read/write FIFO traffic patterns.

  Sequencer

  1. 1.4 · UVM sequencer delivery path — Wire the sequencer to route sequence items from sequence to driver.

  Part 2 · Agent: Driver & Monitor

  Connect software UVM components to hardware FIFO pins.

  Driver basics

  1. 2.1 · Driver: seq_item_port.get_next_item() — Retrieve the next transaction from the sequencer with get_next_item() in run_phase.

  Virtual interface

  1. 2.2 · Virtual interface via uvm_config_db — Pass a virtual interface from tb_top to the driver through uvm_config_db.

  Handshake

  1. 2.3 · Handshake: item_done() and wave analysis — Complete the driver handshake with item_done() and analyze timing on VCD waveforms.

  Monitor

  1. 2.4 · UVM monitor: sample FIFO pins — Sample FIFO interface signals on the clock edge and reconstruct transactions.

  Analysis port

  1. 2.5 · Analysis port: broadcast monitored data — Use analysis ports to broadcast monitored transactions to downstream components.

  Part 3 · Env and Coverage

  Assemble the verification environment, compare data, and hunt coverage.

  UVM agent

  1. 3.1 · UVM agent: active vs passive is_active — Build a reusable agent with is_active to switch between active and passive (monitor-only) modes.

  TLM analysis FIFO

  1. 3.2 · TLM analysis FIFO into the scoreboard — Connect a TLM analysis FIFO between monitor and scoreboard so samples are not lost.

  Scoreboard

  1. 3.3 · UVM scoreboard compare() and uvm_error — Compare expected and actual FIFO transactions and raise uvm_error on mismatch.

  UVM env

  1. 3.4 · UVM env: verification environment pack — Wire agent and scoreboard into a reusable environment in build_phase and connect_phase.

  Subscriber

  1. 3.5 · UVM subscriber and covergroup on analysis port — Encapsulate functional coverage in a subscriber with a FIFO full/empty covergroup on the analysis port.

  CDV mission

  1. 3.6 · CDV: hit FIFO full and reach 100% coverage — Tune sequence constraints to flood writes until the FIFO-full coverpoint hits and LCOV reaches 100%.

  Part 4 · Advanced UVM

  Factory, config objects, virtual sequences, and pipelined drivers for large SoC verification.

  UVM test

  1. 4.1 · UVM test: orchestrate env and sequences — Orchestrate the environment and sequences from a top-level UVM test class.

  Objections

  1. 4.2 · raise_objection / drop_objection time control — Use phase objections to keep run_phase alive until stimulus completes.

  Factory

  1. 4.3 · UVM factory: type_id::create() — Allocate components with type_id::create() instead of new() for flexible substitution.

  Factory override

  1. 4.4 · Factory override: swap in error-injection sequence — Override the factory to replace a normal sequence with an error-injection sequence without editing base code.

  Config object

  1. 4.5 · Configuration object for agent settings — Bundle agent and env settings into one config object and pass it via uvm_config_db.

  Virtual sequence

  1. 4.6 · Virtual sequence: multi-agent fork-join conductor — Coordinate parallel write and read sequences on separate sequencers with a virtual sequence and fork–join.

  Pipelined driver

  1. 4.7 · Pipelined driver: separate get() and put() (AXI prep) — Refactor the driver to use separate get() and put() in parallel threads for AXI-style pipelining.

  Part 5 · AMBA APB and UVM RAL

  APB protocol, register abstraction, and the roadmap to AXI.

  APB protocol

  1. 5.1 · AMBA APB: PSEL, PENABLE, PWRITE timing — Learn APB SETUP/ACCESS timing and verify slave behavior in simulation.

  RAL concept

  1. 5.2 · Why UVM RAL maps registers to objects — Map APB registers (CTRL/STAT/DATA) to uvm_reg objects in a register block.

  RAL adapter

  1. 5.3 · RAL adapter: reg ops to APB bus transactions — Implement a register adapter that translates register operations into APB bus transactions.

  Frontdoor

  1. 5.4 · Mission: reg_model frontdoor write() one-liner — Control APB registers with a single RAL frontdoor write() instead of raw bus sequences.

  RAL coverage

  1. 5.5 · Mission: APB register field coverage 100% — Exercise all APB register fields via UVM RAL and reach 100% field coverage with LCOV.

  AXI roadmap

  1. 5.6 · Next level: AXI masterclass invitation (AXI4-Lite demo) — Contrast AXI4-Lite’s pipelined channels with APB and preview the AXI masterclass path.

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• PRO 30 Lessons AXI CLASS RTLStudio

  AXI Class | RTLStudio

  Pro

  30 lessons · 6 parts · videos coming soon

  Pro AMBA AXI4 design and UVM verification — AXI4-Lite, burst, outstanding/out-of-order, SVA checkers, and a 2×2 interconnect capstone.

  **30 lessons** · about 5 minutes each · roughly 3 hours total

  Full outline (30 lessons)

  Part 0 · AXI Foundation

  Bundle AXI’s five channels into modern SystemVerilog interfaces.

  AXI Protocol Overview

  1. 0.1 · AXI Protocol Overview: VALID/READY handshake — Introduce the AXI VALID/READY handshake and implement a simple synchronous sink in RTL.

  AXI SV Interface and Modport

  1. 0.2 · AXI SV interface and modport: master and slave directions — Bundle AXI signals into an SV interface and define master/slave modport directions.

  Part 1 · AXI4-Lite RTL Design

  Design an AXI4-Lite slave in pure SystemVerilog.

  Write Channels RTL

  1. 1.1 · Write channels (AW, W, B) RTL: AWREADY and WREADY handshake — Implement AXI4-Lite write channel handshake logic for AWREADY and WREADY.

  Read Channels RTL

  1. 1.2 · Read channels (AR, R) RTL: ARREADY and RVALID handshake — Implement read channel handshake for ARREADY and RVALID.

  SV Struct Register Map

  1. 1.3 · SV struct register map: packed CTRL, STAT, and DATA — Define packed structs for CTRL, STAT, and DATA register fields and verify in a testbench.

  AXI4-Lite Slave FSM

  1. 1.4 · AXI4-Lite slave FSM: enum states and case transitions — Control AXI4-Lite transactions with an enum-based FSM and case state transitions.

  Skid Buffer

  1. 1.5 · Skid buffer: decouple VALID/READY timing on an AXI channel — Add a skid buffer on the write data channel to break VALID/READY timing paths under backpressure.

  Part 2 · AXI4-Lite UVM Verification

  Verify the AXI4-Lite DUT with UVM and RAL.

  AXI Sequence Item

  1. 2.1 · AXI sequence item: address, data, and UVM field macros — Define an AXI4-Lite sequence item with address, data, and response fields using UVM field macros.

  AXI Driver

  1. 2.2 · AXI driver: VALID/READY handshake and item_done — Implement AXI4-Lite driver handshake and item_done synchronization.

  AXI Monitor and Scoreboard

  1. 2.3 · AXI monitor and scoreboard: sample bus and compare registers — Passively sample the bus and verify register reads/writes with monitor and scoreboard.

  UVM RAL Adapter for AXI

  1. 2.4 · UVM RAL adapter for AXI: reg2bus and bus2reg — Translate register operations to AXI4-Lite bus transactions via reg2bus and bus2reg.

  Coverage-Driven AXI Verification

  1. 2.5 · Coverage-driven AXI verification: 100% READY backpressure mission — Hit 100% functional coverage on READY backpressure by constraining master-ready delays.

  Part 3 · AXI4 Full RTL Design

  Burst, outstanding, and a BRAM memory bridge.

  AXI4 Burst and Size

  1. 3.1 · AXI4 burst and size: AWLEN and AWSIZE address stepping — Implement burst length and transfer size with AWLEN and AWSIZE address stepping.

  Write Data Channel

  1. 3.2 · Write data channel: WSTRB and WLAST for write bursts — Manage WSTRB, a write beat counter, and WLAST to terminate write bursts.

  Read Data Channel

  1. 3.3 · Read data channel: RLAST on the final read beat — Assert RLAST on the final beat of an AXI4 read burst.

  Outstanding Transactions

  1. 3.4 · Outstanding transactions: AWID tracking FIFO — Track multiple in-flight write transactions with an AWID FIFO.

  Out-of-Order and Interleaving

  1. 3.5 · Out-of-order and interleaving: observe-only routing theory — See how transaction IDs support out-of-order read responses and interleaved write beats.

  AXI4 Slave Memory Controller

  1. 3.6 · AXI4 slave memory controller: BRAM wrapper bridge — Map AXI4 write strobes to BRAM byte enables and verify burst write/readback.

  Part 4 · AXI4 Full UVM Verification

  Five-channel parallel UVM for AXI Full timing.

  Dynamic Array Payload

  1. 4.1 · Dynamic array payload: runtime-sized burst data in the sequence item — Allocate dynamic data/wstrb arrays in sequence items for variable-length bursts.

  Independent Channel Driver

  1. 4.2 · Independent channel driver: fork/join_none on five AXI channels — Drive all five channels in parallel with fork/join_none to avoid deadlocks.

  ID Tracking Monitor

  1. 4.3 · ID tracking monitor: associative array for outstanding transactions — Track outstanding transactions by ID in the monitor for response correlation.

  Out-of-Order Scoreboard

  1. 4.4 · Out-of-order scoreboard: match responses by BID and RID — Match write/read responses to address-phase transactions using BID/RID lookup.

  AXI Virtual Sequence

  1. 4.5 · AXI virtual sequence: parallel read and write traffic — Fork parallel AXI read and write sequences to stress outstanding transaction handling.

  Part 5 · SVA and System Integration

  SVA protocol checkers, multi-master systems, and the capstone.

  SVA Basics for AXI

  1. 5.1 · SVA basics for AXI: stable data while VALID waits for READY — Enforce handshake stability: data and control remain stable while VALID is high and READY is low.

  SVA Burst and ID Checker

  1. 5.2 · SVA burst and ID checker: AWLEN versus WLAST beat count — Assert WLAST occurs when the AWLEN-defined beat count completes.

  AXI Crossbar Interconnect

  1. 5.3 · AXI crossbar interconnect: observe-only routing theory — Introduction to address decoding and round-robin arbitration in multi-master systems.

  Multi-Master Arbitration RTL

  1. 5.4 · Multi-master arbiter RTL: round-robin grant logic — Implement round-robin arbitration for simultaneous master requests.

  AXI Error Handling

  1. 5.5 · AXI error handling: SLVERR and DECERR in UVM sequences — Handle SLVERR/DECERR responses in UVM sequences without fatal exits.

  AXI Exclusive Access

  1. 5.6 · AXI exclusive access: ARLOCK and EXOKAY response handling — Implement and verify exclusive access with ARLOCK and EXOKAY handling.

  The Ultimate AXI System

  1. 5.7 · The ultimate AXI system: 2x2 capstone with UVM, SVA, and 100% coverage — Tune virtual-sequence constraints and arbitration to reach 100% LCOV in a 2-master × 2-slave system.

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• PRO 31 Lessons SOC CLASS RTLStudio

  SoC Class | RTLStudio

  Pro

  31 lessons · 6 parts · videos coming soon

  Pro SoC integration track — memory map and AXI-Lite decode, GPIO/timer/UART/IRQ islands, system control, DMA data movement, and a mini-SoC capstone.

  **31 lessons** · about 5 minutes each · roughly 2.5 hours total

  Full outline (31 lessons)

  Part 0 · SoC Warming Up

  Meet a mini-SoC memory map and walk a pre-built hierarchy in simulation.

  What is a mini-SoC?

  1. 0.1 · What is a mini-SoC? — Introduce SoC memory map constants and verify base address assignments via simulation.

  Explore SoC Hierarchy

  1. 0.2 · Explore a pre-built SoC tree — Explore a pre-seeded SoC hierarchy and verify base address assignments via simulation without code changes.

  Part 1 · Address Map & Decode

  Turn a memory map into combinational decode, one-hot selects, and an AXI-Lite fabric.

  Memory Map Table

  1. 1.1 · Memory map table design — Design localparam memory map bases and region sizes for address decoding.

  Address Hit

  1. 1.2 · Combinational address hit — Implement combinational address hit detection and decode error logic for a simple SoC address map.

  One-Hot Slave Select

  1. 1.3 · One-hot slave select — Implement priority-free one-hot slave select logic from a hit vector in SystemVerilog.

  AXI-Lite Decode Wrapper

  1. 1.4 · AXI-Lite decode wrapper — Implement an AXI-Lite decode wrapper to route AW/AR addresses to multiple slaves and mux B/R responses.

  RW Permission Gates

  1. 1.5 · Read/write permission gates — Implement read/write permission gates and assert SLVERR on access violations.

  Multi-Slave Interconnect

  1. 1.6 · Multi-slave interconnect lite — Integrate the timer CSR slave with the multi-slave interconnect by implementing address decoding and register read/write logic.

  Part 2 · Peripheral Islands

  Build GPIO, timer, UART, and IRQ islands, then wrap them as a peripheral subsystem.

  GPIO CSR Block

  1. 2.1 · GPIO register block — Implement GPIO direction, output, and set/clear registers in a student module and verify with a testbench.

  Timer Tick

  1. 2.2 · Timer / tick generator — Build a timer peripheral with prescaler, counter, and compare match logic to generate periodic interrupt ticks.

  UART CSR Hook

  1. 2.3 · UART CSR hook (lite) — Implement a lightweight UART CSR hook to expose TX data and busy status via AXI-Lite, verifying functionality with a testbench.

  IRQ Status Enable Clear

  1. 2.4 · IRQ status / enable / clear — Implement sticky IRQ status, enable, and clear CSRs using AXI-Lite interface logic.

  IRQ Aggregator

  1. 2.5 · IRQ aggregator (OR tree) — Implement an IRQ aggregator using a reduction OR operator to combine multiple interrupt lines into a single output.

  Peripheral Subsystem Top

  1. 2.6 · Peripheral subsystem top — Integrate GPIO, timer, UART, and IRQ modules into a peripheral subsystem top using AXI interfaces and interrupt aggregation.

  Part 3 · System Control

  Sequence reset, clock enables, boot vector, and watchdog into a sysctrl block.

  Reset Sequencing

  1. 3.1 · Reset sequencing — Implement a reset sequencer that stretches POR for a configurable number of cycles before releasing system and peripheral resets.

  Clock Enables

  1. 3.2 · Clock enables & gating intro — Generate a clock enable signal from an idle indication to reduce power consumption.

  Boot Reset Vector

  1. 3.3 · Boot / reset vector CSR — Implement a boot address latching and soft reset CSR using AXI-Lite, and verify it with a testbench.

  System ID Version

  1. 3.4 · System ID / version regs — Expose read-only chip ID and revision CSRs in the SoC IP.

  Watchdog Tie-In

  1. 3.5 · Watchdog tie-in — Implement watchdog kick CSR and timeout IRQ logic in the SOC IP module.

  Sysctrl Top

  1. 3.6 · System control block top — Integrate reset, clock enable, and CSRs in sysctrl_top by connecting sub-modules and verifying system control signals.

  Part 4 · Data Movement

  Move data with AXI-Stream slices, mem↔stream FIFOs, and a small DMA engine.

  AXIS Register Slice

  1. 4.1 · AXI-Stream register slice — Implement an AXI-Stream register slice to pipeline valid/ready handshakes and verify it with a testbench.

  Mem Stream FIFO Bridge

  1. 4.2 · Mem ↔ stream FIFO bridge — Bridge memory port and AXI-Stream with a small FIFO to decouple data producers and consumers.

  DMA Descriptor CSR

  1. 4.3 · DMA descriptor CSR — Implement SRC/DST/LEN/GO descriptor registers for a DMA controller using AXI4-Lite interface.

  Mem-to-Periph DMA

  1. 4.4 · Memory-to-peripheral DMA — Implement a Memory-to-Peripheral DMA controller that reads from memory and writes to a peripheral port using a finite state machine.

  Periph-to-Mem DMA

  1. 4.5 · Peripheral-to-memory DMA — Implement a state machine to capture peripheral stream data and write it to memory via AXI handshakes.

  DMA Engine Top

  1. 4.6 · DMA engine top — Integrate descriptor CSR and transfer FSMs in dma_engine_top.

  Part 5 · Integration & Capstone

  Tie a CPU stub, decode, peripherals, DMA, and IRQ into a mini-SoC capstone.

  CPU Stub Master

  1. 5.1 · Fixed master CPU stub — Implement a fixed master CPU stub FSM to drive AXI write transactions for GPIO and timer programming.

  Connect Decode and Periph

  1. 5.2 · Connect decode + peripherals — Wire the decode fabric to the peripheral subsystem to enable CPU communication with GPIO and other peripherals.

  Attach DMA and IRQ

  1. 5.3 · Attach DMA + IRQ to fabric — Attach DMA engine and IRQ lines to the SoC fabric by completing port connections in the design module.

  System-Level Testbench

  1. 5.4 · System-level testbench — Construct a system-level testbench to drive a mini-SoC design with directed sequences and verify GPIO/UART integration.

  Mini-SoC Capstone

  1. 5.5 · Ultimate mini-SoC — Integrate a mini-SoC top-level wrapper with GPIO and timer IRQ support, verifying end-to-end functionality via a testbench.

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• PRO 30 Lessons RISC-V CLASS RTLStudio

  RISC-V Core Class | RTLStudio

  Pro

  30 lessons · 6 parts · videos coming soon

  Pro RISC-V RV32I core track — fetch and decode, ALU execute, load/store, CSR and trap/IRQ, and a core capstone in the browser IDE.

  **30 lessons** · about 5 minutes each · roughly 2.5 hours total

  Full outline (30 lessons)

  Part 0 · RV Core Warming Up

  RV32I ISA & register ABI

  1. 0.1 · RV32I ISA and register ABI — Read RV32I ISA opcodes and register ABI constants from rv32_pkg and verify DUT output via simulation.

  $readmemh and first ADD

  1. 0.2 · Load an instruction word and read it back — Preload an instruction word into the instruction memory and verify that the design reads it back correctly.

  Part 1 · Fetch & Decode

  PC, reset, PC+4

  1. 1.1 · Program counter with reset and PC+4 — Implement a 32-bit Program Counter register with reset-to-zero and PC+4 increment logic, verifying the sequential address generation in a testbench.

  Instruction memory port

  1. 1.2 · Instruction memory read port — Implement a word-aligned read port for instruction memory by converting byte addresses to word indices and reading from the memory array.

  Opcode / funct decode

  1. 1.3 · Opcode and funct field decode — Extract opcode, funct3, and register fields from a 32-bit RISC-V instruction word using bit-slicing.

  Immediate I/S/B/U/J

  1. 1.4 · Immediate generator for all five formats — Implement immediate extraction and sign-extension for RISC-V I, S, B, U, and J formats in rv32i_imm.sv.

  Main control decoder

  1. 1.5 · Main control signal decoder — Implement the main control signal decoder for RV32I instructions to generate regwrite, alusrc, and other control signals.

  Fetch-decode top

  1. 1.6 · Fetch and decode integration — Integrate PC, IMEM, decoder, and immediate generator into a fetch-decode stage.

  Part 2 · Execute Path

  Register file x0..x31

  1. 2.1 · Register file with hardwired x0 — Build the 2-read / 1-write integer register file with x0 tied to zero.

  ALU R-type & I-type

  1. 2.2 · ALU for R-type and I-type operations — Implement the combinational ALU for ADD, SUB, AND, OR, XOR, and SLT operations in the RV32I instruction set.

  LUI & AUIPC

  1. 2.3 · LUI and AUIPC upper immediate paths — Route the U-type immediate through the ALU for LUI and AUIPC instructions.

  Branch compare unit

  1. 2.4 · Branch condition compare unit — Implement the branch condition compare logic for RV32I branch instructions (BEQ, BNE, BLT, BGE, BLTU, BGEU) in the rv32i_branch module.

  JAL & JALR target

  1. 2.5 · JAL and JALR target calculation — Compute JAL and JALR jump targets and link addresses by connecting the immediate generator and implementing adder logic.

  Execute datapath top

  1. 2.6 · Execute datapath integration — Connect register file read ports to ALU operands to complete the RV32I execute stage datapath integration.

  Part 3 · Load/Store & Local Memory

  LSU control & byte_en

  1. 3.1 · Load/store control and byte enables — Implement per-byte write enable generation and data alignment logic for the RISC-V Load/Store Unit based on access size and address offset.

  Load + sign extension

  1. 3.2 · Load data sign and zero extension — Implement byte enable signals for sign and zero extension in the RV32I Load/Store Unit.

  Store SB/SH/SW

  1. 3.3 · Store byte, half, and word alignment — Implement store data alignment logic in the RV32I Load/Store Unit to correctly place byte, half, and word data into memory lanes.

  Alignment & misalign flag

  1. 3.4 · Address alignment check — Implement address alignment checks for half-word and word accesses in the RV32I load/store unit to detect misaligned memory operations.

  Data memory (sync RAM)

  1. 3.5 · Local data memory with byte writes — Implement a synchronous-write, combinational-read data RAM with byte enable signals for partial word updates.

  LSU + DMEM top

  1. 3.6 · LSU and data memory integration — Connect the LSU to the local data RAM and run a store followed by a load to verify data integrity.

  Part 4 · CSR, Trap & IRQ Interface

  CSR file (CSRRW/S/C)

  1. 4.1 · Machine CSR file — Implement the Machine CSR read mux for mstatus, mtvec, mepc, and mcause to support read, set, and clear operations in the RV32I core.

  ECALL & trap entry

  1. 4.2 · ECALL trap entry — Implement CSR read logic for mepc, mcause, and mstatus to verify ECALL trap entry behavior in the RISC-V CSR module.

  MRET & mepc restore

  1. 4.3 · MRET and mepc restore — Implement MRET logic to restore MIE from MPIE and expose mepc in the CSR module.

  mcause & mtvec modes

  1. 4.4 · mcause codes and the mtvec base — Program the trap vector base and read back interrupt versus exception causes in the RISC-V CSR module.

  External IRQ input port

  1. 4.5 · External interrupt request port — Qualify the external irq_i port with the mstatus MIE enable bit to control interrupt servicing.

  Trap/IRQ integration top

  1. 4.6 · Trap and interrupt integration — Integrate trap and interrupt handling by redirecting the PC to mtvec on a trap and restoring it from mepc on MRET.

  Part 5 · Core Capstone

  Stitch fetch-exec-LSU

  1. 5.1 · Stitch the single-cycle datapath — Stitch the single-cycle datapath by connecting the RV32I core to instruction and data memories in student/rtl/design.sv and verify execution with the testbench.

  rv32i_core module shell

  1. 5.2 · The rv32i_core module interface — Connect the rv32i_core module to memory interfaces and verify execution of a simple program.

  Core TB: fibonacci loop

  1. 5.3 · Core testbench with a fibonacci loop — Preload a Fibonacci loop into the RV32I core's instruction memory and verify the computed result in debug_x10.

  Ultimate rv32i_core

  1. 5.4 · Ultimate rv32i_core capstone — Integrate the RV32I core with memory and verify end-to-end execution of a sum loop and ECALL.

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• PRO 30 Lessons RV SYS CLASS RTLStudio

  RISC-V System Class | RTLStudio

  Pro

  30 lessons · 6 parts · videos coming soon

  Pro RISC-V system track — core on AXI-Lite MMIO, peripheral programs, interrupts and DMA, pipeline, and a system capstone.

  **30 lessons** · about 5 minutes each · roughly 2.5 hours total

  Full outline (30 lessons)

  Part 0 · Platform Recap

  SoC map & mini_soc tour

  1. 0.1 · SoC platform tour — Tour the SoC memory map constants and RV32I opcodes, verifying the DUT routes them correctly via the testbench.

  Replace stub with rv32i_core

  1. 0.2 · Stub to core swap — Swap the fixed cpu_stub master for rv32i_core_bus and prove it runs.

  Part 1 · Core on Bus (MMIO)

  LSU to AXI-Lite master FSM

  1. 1.1 · LSU AXI-Lite master — Implement the reset logic for an AXI4-Lite master FSM to initialize state and data registers for RISC-V load/store operations.

  Connect to soc decode fabric

  1. 1.2 · Connect soc decode — Connect the RV32I core master to the SoC interconnect and route requests to every peripheral to enable memory-mapped I/O access.

  MMIO load/store timing

  1. 1.3 · MMIO load store — Measure MMIO store and load latency by connecting AXI interfaces in the design and verifying results in the testbench.

  ROM/RAM/CSR region map

  1. 1.4 · ROM RAM CSR map — Classify memory addresses into RAM, MMIO, or unmapped holes using a memory map table and address decoder.

  Link script to .hex layout

  1. 1.5 · Link script hex — Load a program image from tb/programs into the instruction ROM and connect peripheral signals in the testbench.

  Bus + MMIO subsystem top

  1. 1.6 · Bus MMIO top — Assemble the RV32I core, interconnect, and peripheral island into one subsystem by wiring the AXI bus interfaces in the top-level design.

  Part 2 · Peripheral Programs

  GPIO output .hex

  1. 2.1 · GPIO output hex — Connect GPIO ports and load program image to drive hex output pattern 0xAA.

  GPIO input poll loop

  1. 2.2 · GPIO input poll — Complete the GPIO input poll by connecting testbench signals and loading the program hex file.

  Timer delay loop

  1. 2.3 · Timer delay loop — Enable the timer from software and read its control register back to verify peripheral configuration.

  UART status poll TX

  1. 2.4 · UART status TX — Connect GPIO ports and load UART program to verify status-based TX transmission.

  Multi-peripheral sequence

  1. 2.5 · Multi-periph sequence — Complete the testbench port connections and program load for a multi-peripheral RISC-V sequence to verify GPIO, UART, and timer interactions.

  Program integration lab

  1. 2.6 · Program integration lab — Integrate RISC-V core with GPIO, timer, and UART peripherals by configuring AXI address widths and verifying program execution via simulation.

  Part 3 · Interrupts & DMA

  IRQ vector table .hex

  1. 3.1 · IRQ vector table — Place a trap handler at the mtvec word index of the program image to handle interrupts correctly.

  Timer IRQ handler

  1. 3.2 · Timer IRQ handler — Configure timer interrupts and implement the handler to toggle GPIO outputs.

  Sticky IRQ status and clear

  1. 3.3 · GPIO IRQ change — Clear a sticky peripheral IRQ status bit from inside the handler by setting AXI address widths.

  DMA descriptor kick (CSR)

  1. 3.4 · DMA descriptor kick — Program DMA descriptor registers and pulse GO from software to trigger a memory-to-peripheral transfer.

  Core idle + DMA fill

  1. 3.5 · Core idle DMA fill — Verify DMA memory fill operation with CPU idle state and interrupt handling.

  IRQ + DMA subsystem top

  1. 3.6 · IRQ DMA top — Integrate a complete SoC platform with DMA and interrupt support by configuring AXI interface parameters and verifying system-level behavior.

  Part 4 · Pipeline

  Single-cycle vs pipeline

  1. 4.1 · Single vs pipeline — Compare the cycle cost of a single-cycle core against a five-stage pipeline to understand fill overhead.

  IF/ID pipeline registers

  1. 4.2 · IF ID pipeline regs — Build the IF/ID pipeline register to latch the fetched PC and instruction, handling stalls and resets.

  EX/MEM/WB stages

  1. 4.3 · EX MEM WB stages — Complete the IF/ID pipeline register connections in the RV32I pipelined core to ensure correct instruction flow from fetch to decode.

  Data hazard detect

  1. 4.4 · Data hazard detect — Implement a hazard detection unit to detect read-after-write hazards and generate stall/flush signals for a pipelined RISC-V core.

  Forwarding unit

  1. 4.5 · Forwarding unit — Implement the forwarding unit logic to select EX operands from MEM or WB stages, handling priority and x0 exceptions.

  Load-use stall & flush

  1. 4.6 · Load-use stall flush — Implement load-use stall and branch flush logic in the RV32I hazard unit to control the IF/ID register.

  Part 5 · System Capstone

  rv32_soc_top hierarchy

  1. 5.1 · rv32_soc_top — Package the reset sequencer, fabric, peripherals, DMA, and core as one chip top.

  Pipeline core option mux

  1. 5.2 · Pipeline core option — Pass the PIPELINE parameter from the chip top to the SoC platform to select the core flavor.

  End-to-end system TB

  1. 5.3 · System e2e TB — Drive the rv32_soc_top platform from a SystemVerilog testbench to verify end-to-end system behavior by instantiating the design and connecting all interface signals.

  Ultimate rv32_soc

  1. 5.4 · Ultimate rv32_soc — Capstone lesson integrating RV32I core with GPIO, UART, and timer interrupts in the rv32_soc_top platform.

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Free examples

• Quick start — FSM counter
• Hello simulation
• UART transmitter

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