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A 16-word by 16-bit synchronous RAM with independent write/read clocks and 2-bit byte enable support. Features active-low reset and registered read output for timing closure.
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16-word by 8-bit synchronous RAM with independent write/read clocks and registered read output. No reset logic included.
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A configurable 32-bit asynchronous FIFO using AXI4-Stream interfaces and Gray code pointers for safe cross-clock-domain data transfer.
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A 32-bit register with independent byte-write enables for partial updates.
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32-word by 16-bit synchronous single-port RAM with combinational read.
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A 4-deep by 8-bit wide register file with synchronous write and combinational read ports.
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Four-word 8-bit single-port RAM with async reset clear, synchronous write, and combinational read.
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256x64 dual-port RAM with byte-enable masking and combinational reads.
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An 8-bit depth-1 skid buffer that absorbs backpressure by holding data until the consumer is ready. It asserts ready_in only when empty and maintains valid_out until valid_in deasserts.
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8x16 Single-Port Synchronous RAM with byte write enable. Depth: 8 words, Width: 16 bits. Read is synchronous (data available on next clock edge after address). Write is synchronous (data written on rising edge if we_n is low).
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An 8-deep, 32-bit wide register file with one synchronous write port and two independent combinational read ports.
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8-bit wide, 8-depth synchronous single-port RAM with write-first read behavior and asynchronous reset.
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Asymmetric RAM with 8-bit write, 16-bit read, byte-enable, and invalidate-to-shadow functionality.
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8x32 register file with byte-enable write support and shadow commit mechanism for atomic updates.
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A 4-entry, 8-bit Content-Addressable Memory with individual entry invalidate capability.
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A synchronous circular buffer with 16 entries and 8-bit data width supporting push/pop operations with full/empty flags.
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Single-clock FIFO that tracks occupancy with an explicit count register, exposes wready/rvalid on both producer and consumer sides, and defaults to depth 64 with 16-bit data.
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A credit-based flow control module that manages ready/valid handshakes with a maximum of 4 credits.
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Dual-Port RAM with write-first bypass on Port A and shadow buffer read with invalidation on Port B.
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Dual-Port Register File 4x16 with Invalidate, Shadow Commit, Byte Enable, and Hazard Detection for L2 upgrades.
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First-Word-Fall-Through synchronous FIFO with 16x8 depth and programmable almost-full/empty thresholds.
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A First-Word-Fall-Through (FWFT) synchronous FIFO module with configurable almost full and almost empty threshold flags for precise flow control.
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Synchronous LIFO stack with depth 8, 8-bit data width, full/empty flags, and overflow/underflow protection.
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An 8x8 double-buffering module that swaps between two memory banks on a frame pulse for continuous data streaming.
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Compact single-clock FIFO using extra-bit read/write pointers for full/empty detection, enable-style w_en/r_en ports, synchronous flush, and default depth 16 with 32-bit data.
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True dual-clock 1-write-2-read register file with 8x16 depth and registered read output.
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An 8x16 register file with shadow buffer support for speculative writes, atomic commit, and abort capabilities.
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A registered Read-Only Memory with 64 words of 8 bits and an active-low output enable signal.
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A combinational ROM with 16 words of 8 bits, mapping 4-bit addresses to their hex values.
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Simple CAM 4-Entry x 8-Bit with search, write, and invalidate operations for L2 cache tag lookup.
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A 2-deep skid buffer for 8-bit stream data that handles back-pressure and stalls.
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A synchronous FIFO module with 64-bit data width, configurable depth, and status flags for full, empty, almost full, and almost empty conditions.
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A synchronous FIFO depth calculator using a counter-based approach to track buffer levels with configurable almost-full thresholds.
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True dual-port RAM with independent write and read clock domains, 8 words x 8 bits, synchronous reset.
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4-word by 8-bit register file with write-priority, bit-masking, hold, and park controls.
