Open IP

A basic 2-input AND gate implemented in Verilog.

A basic 2-input NAND gate implemented in Verilog.

A simple 2-input NOR gate module for combinational logic.

A basic 2-input OR gate implemented in Verilog for digital logic design.

Basic 2-input XOR logic gate implementation in Verilog.

A configurable-width combinational module that performs a bitwise NOR operation on three input vectors.

Combinational logic module that outputs the majority value of three binary inputs.

A synchronous 3-state buffer with enable control and active-low reset, outputting High-Z when disabled.

Combinational 5-input majority voter with a tie flag for boundary cases.

An 8-bit combinational logic gate that performs bitwise XNOR operations on two input vectors.

Computes the NAND of all bits in an 8-bit input vector.

Combinational logic that outputs high when 5 or more of 8 inputs are high.

An 8-bit combinational logic module that performs bitwise AND or OR operations based on a mode select signal.

Combinational 8-bit OR-reduce gate producing a single output bit.

Generates a mask of all bits strictly below the highest set bit in an 8-bit request vector.

An 8-bit XOR-reduce tree that computes the parity of an 8-bit input vector using a hierarchical binary tree structure.

4:1 Priority Mux with Valid/Skid Buffer for L1 Cache Upgrade

Combinational 16:1 mux with sixteen 32-bit inputs and a 4-bit select.

Latch-free combinational 32-bit 2:1 mux with no clock, reset, or enable.

Combinational 4:1 mux with four 3-bit inputs and a 2-bit select.

Combinational 4:1 mux with 8-bit inputs; active-high enable forces zero output.

Combinational 8:1 mux selecting one of eight 32-bit words when enabled.

A glitch-free 2:1 clock multiplexer that synchronizes selection signals to prevent output glitches during clock source switching.

Registered 8-to-1 multiplexer with one-hot select encoding and enable control.

Registered 2:1 mux with packed 2-bit din bus, active-high enable, and active-low reset.

Registered 16:1 mux with active-low enable and synchronous capture on clk.

Canonical registered 2:1 lesson IP — synchronous 8-bit mux with enable and active-low reset.

16-bit cycle counter with prescaler, load enable, match interrupt, and synchronous reset.

4-Bit Counter Match Pulse

A 4-bit free-running counter with synchronous enable, load, and a wrap strobe output that pulses when the count rolls over from 15 to 0.

Synchronous 4-bit down counter with asynchronous reset, parallel load, and enable control.

Synchronous 4-digit BCD counter with up/down control, load, and carry/borrow flags.

8-Bit Binary Up Counter with load enable and match interrupt request generation.

8-Bit Johnson Counter with parallel load, count enable, and match-based interrupt generation.

An 8-bit leading zero counter with synchronous load, enable, and match interrupt generation.

An 8-bit ring counter with synchronous load and circular right shift functionality.

An 8-bit up/down counter with synchronous load and asynchronous reset.

Bidirectional Counter 4-Bit with load enable and match interrupt generation.

A 1-digit Decade BCD counter with synchronous load, enable, and asynchronous reset.

An 8-bit counter with dual compare-match outputs and an interrupt request signal.

16-bit event counter with rising-edge detection and synchronous capture register.

An 8-bit binary counter with pipelined Gray-code conversion, supporting load, enable, and backpressure.

A fully synthesizable 4-bit up counter with synchronous load, enable, and asynchronous reset capabilities.

Fully synthesizable 8-bit loadable down counter with match and zero interrupt requests.

A parameterized modulo-N counter with asynchronous reset and terminal count output.

Parameterized N-Bit Counter with Enable, Wrap, Load, Match IRQ

An 8-bit counter with load enable, match-based IRQ, and sticky overflow detection for L1/L2 upgrades.

16-bit register with mutually exclusive modes: parallel load, shift left, and shift right.

Combinational 32-bit barrel with op encoding: pass-through, logical left, logical right, and rotate left.

A combinational 32-bit funnel shifter that concatenates two 32-bit inputs and shifts them left to extract a 32-bit window.

A 32-bit barrel shifter supporting logical, arithmetic, and serial shift operations with parallel load capability.

8-bit registered barrel shifter and rotator with support for logical, arithmetic, and serial shift modes.

8-Bit Bit Reversal with registered output, enable control, and sticky error flag.

8-bit bit reversal module with parallel and serial input modes and registered output.

Registered 8-bit byte-swap module with enable and valid handshake for endianness conversion.

Converts 8-bit parallel input to LSB-first serial output with busy flag and synchronous load.

8-Bit unidirectional shift register with parallel load and serial input support for logical and arithmetic shift-right operations.

Arithmetic right shift module with Valid/Ready handshake for 8-bit signed data.

Extracts an 8-bit field from a 16-bit input word using a barrel shifter and mask.

Combinational module to insert a variable-width field into a 32-bit data word at a specified offset.

Combinational module that rotates a 32-bit word by 0 to 3 bytes.

Combinational module performing circular left shift on 8-bit data with variable shift amount.

A single-slot valid/ready handshake buffer for 16-bit data with backpressure support.

A 16-bit nibble interleave module that reverses nibble order with skid buffer support for backpressure handling.

16-bit shift/rotate module supporting LSR, LSL, Nibble Rotate Right, and Arithmetic Shift Right with registered output.

8-bit serial-in shift register with parallel load, supporting left/right shift modes and serial data injection.

An 8-bit universal shift register supporting parallel load, bidirectional serial shifting, and valid status output.

16-bit priority encoder with registered outputs and Valid/Ready skid buffer for backpressure handling.

A 4-bit BCD to binary converter with Valid/Ready interface and skid buffer for backpressure handling.

A synchronous 4-bit binary to BCD converter using the shift-and-add-3 algorithm with FSM control.

Converts a 4-bit thermometer code to a 2-bit binary value with clamping for overflow.

Encodes a 3-bit binary input into an 8-bit one-hot output.

An 8-bit priority decoder that converts one-hot input to binary index, featuring registered output, valid/ready interface, and skid buffer for backpressure handling.

Combinational priority encoder converting 8-bit thermometer code to 3-bit binary index with MSB priority.

Combinational logic module that sign-extends an 8-bit input to a 16-bit output by replicating the MSB.

Registered 8-to-16 bit zero extension with enable control and valid handshake.

Glitch-free 4-bit Binary to Excess-3 converter with Valid/Ready skid buffer for backpressure handling.

Generate-for compare converter from 8-bit binary to a 9-bit thermometer code slice.

A registered 4-bit to 15-bit thermometer code converter with valid/ready interface and skid buffer for backpressure handling.

Registered 8-bit Gray code incrementer with Gray-to-binary and binary-to-Gray conversion logic.

Converts N-bit Gray code input to corresponding Binary output using a combinational XOR reduction chain.

N-bit priority encoder with registered output and valid/ready skid buffer for flow control.

A registered one-hot to binary decoder with valid/ready handshaking and skid buffer for backpressure handling.

Registered 8-to-3 one-hot to binary encoder with MSB priority and validity check.

Synchronous 8-bit register performing bidirectional Gray code and Binary code conversion with enable and reset controls.

Registered pipelined thermometer-to-binary encoder for 8-bit inputs with valid flag synchronization.

A pipelined module that converts a 16-bit thermometer code into a 4-bit binary index.

Registered pipeline for encoding the index of the first trailing one in an 8-bit input vector.

4-Bit Parity OK Checker with XOR reduction, syndrome-based single-bit error correction, and sticky error flag.

Generates even parity for 8-bit data and latches a sticky error flag for odd parity occurrences.

An 8-bit parity error counter that accumulates odd parity errors in data streams. It supports scrubbing with external data and direct accumulator loading for testing.

Combinational even/odd parity generator using explicit even-parity XOR and mode mux.

SECDED byte-strobe parity scrubber for 32-bit data with SBE/MBE detection.

Hamming(16,11) single-bit error correction module for 16-bit buses with syndrome-based detection and registered output.

Glitch-free registered Hamming distance calculator for 8-bit vectors using $countones.

8-bit parity checker with selectable odd/even mode, LSB correction, and sticky error flag.

8-bit parity checker with sticky error flag and syndrome-based single-bit correction using data[2:0] as index.

8-bit parity checker with invert-select control and sticky error detection for single-bit error assumption.

An 8-bit register with 2-bit parity syndrome for single-bit error correction and detection.

Single Error Correction Double Error Detection Hamming check for 13-bit codewords.

Toy SECDED syndrome calculator for 4-bit nibbles with invalidate and shadow commit support.

Sticky Parity Error Flag 8-Bit — L1 Upgrade

Balanced XOR-reduction tree computing even parity for a 16-bit input vector.

A synchronous arbiter that locks the grant to the winning request until that request deasserts, with a fixed tie-break preference for request 0.

A combinational static priority arbiter for two request lines where req0 has higher priority than req1.

4-Channel Oldest-First (FIFO) Arbiter with almost-full flag and flush support.

A 4-channel round-robin arbiter with priority rotation to ensure fair access to shared resources.

A 4-input sliding window arbiter with weighted priority, masking, parking, and hold capabilities for fair resource allocation.

A 4-bit priority grant module that selects the lowest-index active request after applying a mask.

Fair-share arbiter with grant-lock and credit-based backpressure for two requests.

Fixed-priority 4-request arbiter with mask, hold, grant-lock, and credit/almost-full.

A 4-input fixed-priority arbiter with a grant mask to disable specific requests dynamically.

4-request Grant-Hold Arbiter with maskable hold and fixed priority fallback.

4-input LRU arbiter with weight masking, park mode, and hold lock functionality.

A lock-free arbiter that grants access to the lowest-priority active request and holds the grant until acknowledgment, supporting backpressure.

4-port Least-Recently-Granted matrix arbiter with round-robin fairness.

A 4-channel sticky round-robin arbiter that holds the grant until acknowledgment, then advances the pointer.

A 4-input token-ring arbiter that rotates a one-hot grant token to the next active requester, ensuring fair access.

Weighted Priority Arbiter with Mask, Park, and Hold Lock for 4 requests.

4-input Weighted Round-Robin Arbiter with masking and Park-on-Grant strategy.

A 2-bit edge detector with configurable rising/falling edge selection, programmable window timer, hold mode, and sticky flag for event latching.

8-Bit Sticky OR Accumulator with configurable window clear and explicit reset capabilities.

Both-edge detector with N-cycle hold pulse generation.

Ensures output pulse width is at least min_width cycles using synchronous reset and single clock domain.

Passes first pulse, rejects subsequent pulses within N cycles.

8-bit edge counter with windowed sticky flag, load enable, and clear functionality.

Edge-Triggered Single-Cycle Pulse Generator with configurable window width and sticky flag.

Detects a falling edge on sig_in and asserts sig_out for a configurable number of clock cycles defined by hold_n.

Module that detects level changes on a single bit, sets a persistent sticky flag, and activates a programmable window timer on each change.

Converts a level signal to a pulse with a configurable hold window and sticky edge flag.

Filters input pulses to ensure they meet a minimum width of N clock cycles.

Detects if the time interval between consecutive input pulses exceeds a configurable 8-bit threshold.

Measures the width of an input pulse in clock cycles and latches the result.

Quadrature Decoder x4 with windowed sticky inactivity flag.

8-bit rising-edge event counter with load, clear, windowing, and sticky flag support.

Rising-Edge Hold for N Cycles with configurable window and sticky rearm capability.

A single-cycle pulse generator that detects both positive and negative edges, gated by an enable signal and constrained by a configurable window duration. Includes a sticky flag for event latching.

A synchronized debouncer that filters noisy input signals and provides clean edge detection pulses.

A combinational 1-bit full adder that computes sum and carry-out from three input bits.

1-Bit Full Adder with saturation clamping and sticky signed overflow flag.

A basic 1-bit half adder module that computes sum and carry from two input bits.

A 16-bit carry-select adder that splits addition into two 8-bit blocks to reduce propagation delay.

A synchronous 16-bit two's complement signed adder with overflow detection logic.

A 2-bit saturating up/down counter with Gray code output and parallel load capability.

Combinational module that counts the number of leading zeros in a 32-bit input vector using a priority encoder approach.

Registered 32-bit equality comparator with sticky saturation flag for underflow detection.

Registered 32-bit population counter with sticky saturation flag and clear capability.

A 4-bit arithmetic unit supporting addition and subtraction with signed overflow detection using two's complement logic.

A synchronous 4-digit BCD adder with carry propagation and a sticky saturation flag for overflow detection.

4-input 8-bit adder tree with saturating arithmetic and sticky overflow flag.

Registered 8-bit absolute value calculator with sticky overflow detection for -128.

An 8-bit ALU slice supporting AND, OR, XOR, and unsigned addition with a sticky saturation flag for overflow detection.

8-bit carry-save adder with signed saturation clamping and sticky saturation flag.

Registered 8-bit Count Trailing Zeros unit with valid handshake and sticky saturation flag.

8-bit registered comparator with equality, greater-than, less-than outputs and a sticky saturation flag.

Combinational 8-bit incrementer with carry-out detection.

Registered 8-bit magnitude comparator with sticky saturation flags for tracking historical comparison states.

8-Bit Min/Max Comparator with sticky saturation flag and synchronous clear.

8-bit one's complement adder with end-around carry, saturation clamping, and sticky overflow flag.

An 8-bit unsigned adder with configurable saturation and overflow detection.

8-bit unsigned saturating subtractor with sticky underflow flag, asynchronous reset, and synchronous clear.

An 8-bit synchronous subtractor with borrow-in and borrow-out support for unsigned and signed arithmetic.

8-bit saturating subtractor with sticky underflow flag, asynchronous reset, and synchronous clear.

8x8 Multiply-Accumulate unit with 16-bit accumulator, sticky saturation flag, and clear input.

Glitch-free 8-bit absolute difference calculator with sticky saturation flag and registered outputs.

A 4-digit Binary Coded Decimal subtractor with sticky saturation flag and underflow detection.

Combinational radix-4 Booth signed 4x4 multiplier with explicit partial-product recoding (not a single $signed multiply).

4-bit unsigned carry-lookahead adder with immediate saturation flag and sticky latched saturation flag for overflow monitoring.

Registered signed 8-bit clamp with sticky saturation flag and explicit clear.

Parameterized combinational Kogge-Stone adder with carry-in, carry-out, and signed overflow detection.

Tracks min/max of 8-bit input stream with configurable window-based sticky IRQ generation.

A fully parameterized Verilog ripple-carry adder with carry-in, carry-out, and signed overflow detection.

8-bit adder with registered output, saturation clamping, and sticky saturation flag.

Signed Multiply-Accumulate unit with 4-bit inputs, 8-bit output, saturation arithmetic, and a sticky saturation flag.

4-bit by 4-bit saturating multiplier with sticky saturation flag and clear capability.

Signed 16-bit to 8-bit saturating cast with sticky overflow flag for range safety.

Registered 3-way signed comparator for 8-bit operands with enable and reset.

16-bit Fibonacci Linear Feedback Shift Register with left-shift architecture, fixed taps (x^16+x^15+x^13+x^4+1), and zero-state lock detection.

A 32-bit Fibonacci Linear Feedback Shift Register with right-shift architecture, enable control, and golden-value lock detection.

64-bit LFSR with parameter TAP_SEL choosing between two fixed tap sets, plus load and enable.

An 8-bit Fibonacci Linear Feedback Shift Register supporting right-shift, mask XOR feedback, load, and arithmetic increment modes.

8-bit Galois LFSR with parallel load/shift enables using polynomial x^8+x^6+x^5+x^4+1.

8-bit parallel scrambler with LFSR state, shadow register, invalidate, and byte-enable features.

A 16-bit Additive Lagged Fibonacci pseudo-random number generator with taps j=3 and k=5.

CRC-16-CCITT Serial

Byte-serial CRC-32 generator with Ethernet-style polynomial, init 0xFFFFFFFF, and zlib-compatible output.

A SystemVerilog module that checks incoming data against a PRBS32 sequence generated by an LFSR. It counts bit errors and asserts a persistent error flag.

A 32-bit Pseudo-Random Binary Sequence generator using the IEEE 802.3 polynomial. Supports synchronous reset, enable control, and seed reload for deterministic testing.

A simplified Trivium-Lite NFSR generating 8-bit keystream from an 80-bit state.

32-bit Xorshift pseudo-random number generator with reference-based stall and lock detection.

64-bit Xorshift pseudo-random number generator with seed loading and enable control.

A registered delay element that holds input data for one clock cycle with asynchronous reset and synchronous enable.

16-bit DDS phase accumulator with dual phase output, freeze, and stretch control.

A simple toggle flip-flop that divides the input clock frequency by two.

Glitch-free 4-phase clock-enable sequencer with configurable M/N division counters.

Latch-free, fully synthesizable clock divider with burst, freeze, and clear capabilities. Uses m, n, and div inputs in the comparison logic to ensure no unused ports.

Generates a single-cycle clock enable pulse every N clock cycles when enabled.

Configurable clock enable generator with stretch and phase offset capabilities for precise timing control.

Glitch-free clock enable divider with M/N inputs. Generates a pulse on ce_out when counter reaches M-1. Counter resets when reaching N-1. M must be <= N.

Configurable clock-enable stretcher with busy-handshaking support and m/n ratio control.

A divide-by-3 clock generator that produces a 50% duty cycle output using a 2-bit state machine.

Dual-edge DDR sampler with configurable clock division and enable control.

Duty-correct divide-by-N using M/N ratio with enable and registered output.

Synthesizable fractional clock divider using phase accumulation for low jitter.

Fractional Clock Enable M/N with Used-MN Indicator using Bresenham accumulator.

Glitch-free clock selector with busy indicator for two asynchronous clock sources.

Parameterized integer clock divider with 50% duty cycle supporting even divisors from 2 to 255.

Dual-phase lost-clock detector with configurable threshold and count enable.

A parameterized clock enable generator that produces a periodic enable pulse based on M/N division parameters, with global reset and enable control.

Converts an asynchronous pulse into a glitch-free toggled clock output with configurable duty cycle and enable control.

Generates a busy signal for a configurable number of clock cycles triggered by a start pulse.

Asserts a ready signal after a configurable number of clock cycles following reset.

Combinational logic module that decodes 4-bit hexadecimal inputs into 7-segment display signals with configurable active-high or active-low polarity.

A 4b/6b Run-Length Limited encoder and decoder with disparity control for DC balance.

8-Bit Differential Encoder/Decoder with Stream Enable and Lock Detect

Streaming Huffman encoder for 8-bit symbols using a precomputed static code table and ready/valid handshakes.

An 8-bit parallel-to-serial Manchester encoder with Ready/Valid handshake and backpressure support.

8-bit nibble-swap endian converter with registered outputs, stream enable, and lock detect for identical nibbles.

Combinational 8-bit parallel descrambler using a fixed XOR mask to reverse scrambling operations.

An 8-bit Run-Length Decoder that repeats an input value for a specified count.

A dual-mode 8b/10b encoder and decoder with running disparity support and control character handling.

8-bit additive scrambler with sync lock detection using standard LFSR polynomial.

Bit unstuffer with stream enable and lock detect for serial data integrity.

Fully synthesizable Golay (24,12) block encoder with streaming interface and syndrome calculation.

A synchronous Hamming (7,4) error-correcting decoder that detects and corrects single-bit errors in a 7-bit codeword, outputting the corrected 4-bit data.

Hamming (7,4) Encoder

Inserts a zero bit after five consecutive one bits in a serial data stream for HDLC framing.

Removes stuffed zero bits from an HDLC serial data stream after five consecutive ones.

Pipelined NRZ-to-NRZI line encoder with backpressure support.

Converts NRZI encoded signals to standard NRZ format by detecting transitions.

A Reed-Solomon encoder for 8-bit symbols using GF(2^8) arithmetic with generator polynomial x^2 + 0x03*x + 0x02.

Implements 8b/10b encoding with DC balance and run-length constraints using deterministic lookup tables.

An 8-bit scrambler using a Galois LFSR with polynomial x^8 + x^6 + x^5 + x^4 + 1. It XORs input data with the LFSR state for data randomization.

Combinational module that decodes a 2-bit opcode into separate Read, Write, and Illegal status signals.

Combinational 2-bit to 4-slot one-hot chip-select decoder with global enable.

Combinational module for 8-bit address range matching using base and mask inputs.

An 8-bit register that holds its output value when a stall signal is asserted and loads new data when the stall signal is deasserted.

A single-cycle valid/ready register slice for 8-bit data paths with backpressure handling.

Combinational logic for merging 8-bit data using a byte mask.

A simple AHB-Lite master controller for SystemVerilog designs supporting single-cycle transactions.

Minimal AHB-Lite master that issues one read or write transfer per request.

Single-beat AHB-Lite slave with configurable address range, combinational read response, and write capture on full-word granularity.

APB3 master with setup/access phases and one outstanding transaction.

A fully compliant APB3 master controller supporting single and burst transactions with auto-increment and backpressure handling.

Configurable APB3 slave with word-aligned register file, byte-lane writes, and zero-wait-state PREADY.

A SystemVerilog IP core implementing a slave AXI-Lite interface with a 4-register bank and byte strobe support.

AXI4-Lite slave with 4 read-only registers and ignored write channels.

AXI4-Lite compliant write-only slave with 4 registers and byte enable support. Read accesses return DECERR.

AXI-Stream 1-to-2 Demux routing TDATA/TKEEP/TLAST based on TDEST[0]

AXI-Stream Broadcast 1-to-2 with AND-ready policy

AXI-Stream 2-to-1 multiplexer with priority arbitration and TLAST preservation.

AXI-Stream Register Slice with Retry/Timeout/Error Decode

Single-entry skid buffer for AXI-Stream interfaces to handle backpressure.

Counts Start-of-Frame beats in an AXI-Stream interface with skid buffer support.

AXI4-Lite Simple Master (Single Beat)

A basic AXI4-Lite slave module implementing a 4x32-bit register file with standard handshake protocols.

Registers valid signal and data until acknowledgment is received.

Wishbone B3 master for classic single-beat read/write transactions.

32-bit Wishbone B3 slave with combinational ack and a small register file.

Wishbone B3 Slave with 4x32-bit registers and wait cycle timeout detection.

Converts Wishbone B3 master transactions into AHB-Lite master transactions for single-word transfers.

A Wishbone B.4 compliant slave module with byte-strobe support and a 256-byte internal memory map.

A Wishbone Classic slave module that supports the Retry (RTY) response mechanism for handling busy states during read and write transactions.

Converts Wishbone Classic slave interface to Wishbone Pipelined master interface for protocol bridging.

Wishbone Simple Master with configurable retry and timeout logic for handling slave stalls and errors.

Wishbone slave with 4 registers, retry for invalid addresses, and timeout detection to prevent bus deadlocks.

Single-cycle Wishbone B3 slave bridging to a configurable array of 32-bit CSRs with byte-select write support.

A robust 1-bit handshake protocol for crossing clock domains ensuring reliable data transfer without loss.

Synchronizes an asynchronous active-low reset signal to a synchronous clock domain using a 3-stage flip-flop chain to minimize metastability.

A 4-bit bus synchronizer using a two-stage flip-flop per bit to safely transfer asynchronous signals into a synchronous domain.

4-bit Gray code bus synchronizer with Valid/Ready handshake for asynchronous clock domain crossing.

Crosses a single-cycle pulse from src_clk to dst_clk using a req/ack toggle handshake.

Asynchronous set, synchronous clear flag with credit-based flow control for pulse transfer across clock domains.

2-stage asynchronous reset synchronizer chain for safe Gray-coded FIFO pointer synchronization across clock domains with active-low reset handling.

Dual-clock domain crossing for single-cycle pulses with credit-based flow control.

Enable Level Synchronizer with Busy Hold for CDC

A 16-bit cross-domain clock synchronizer using a four-phase handshake protocol with backpressure support.

Reliable asynchronous clock domain crossing using a two-way handshake protocol for 8-bit data payloads.

Synchronizes an 8-bit bus using a two-flop synchronizer chain per bit — educational follow-on to single-bit two_ff_sync.

Cross-clock domain synchronizer for multi-bit select signals using Gray code encoding to prevent metastability glitches.

Implements a pulse-acknowledgment round-trip mechanism across two asynchronous clock domains to ensure reliable single-cycle pulse transmission and acknowledgment.

Asynchronous clock domain crossing module for 8-bit payloads using Req/Ack handshake with backpressure.

Transfers a single-clock-cycle pulse across asynchronous clock domains using a 2-FF synchronizer, edge detector, and pulse stretcher. Supports clock ratios up to 10:1 and variable reset polarity.

Samples data on a rising edge of a synchronized slow enable signal in a fast clock domain.

Captures a 4-bit data bus synchronized to a destination clock domain using a toggle mechanism and 2-stage synchronizer.

Clock Domain Crossing module that transfers an 8-bit payload using a synchronized toggle signal for handshaking.

Toggle synchronizer with 4-bit payload hold for asynchronous clock domain crossing.

Bidirectional toggle synchronizer with request and acknowledge paths for asynchronous clock domains.

Two-flip-flop CDC synchronizer with async reset stretching for source and destination domains.

Parameterized two-stage synchronizer for single-bit asynchronous signal crossing with optional async reset support.

Configurable tick generator with sticky interrupt capture and enable control.

A 16-bit down-counter with configurable match value, sticky IRQ generation, and immediate match detection on load-zero.

16-bit programmable prescaler with byte-enable masking, sticky IRQ, and capture logic.

A 16-bit down-counter timer with interrupt generation and immediate invalidation support.

Glitch-free 16-bit PWM with shadow registers for dynamic period/duty updates, active-high output, and full verification.

A 32-bit down-counter interval timer that generates an interrupt request upon expiration, supporting preload, enable, and acknowledge signals.

A 32-bit watchdog timer with kick reload, runtime timeout reprogramming, and configurable reset pulse width.

An 8-bit down counter with synchronous load, match-zero pulse detection, and a sticky interrupt request flag.

8-Bit Programmable Digital Deglitch Filter with Sticky IRQ Capture for both-edge sampling and noise immunity.

8-Bit Window Comparator with sticky IRQ capture and synchronous clear.

Eight-channel 16-bit PWM with global period, per-channel duty, edge/center-aligned modes, and a simplified APB-like register interface.

Captures 8-bit activity signals and generates a sticky IRQ and timeout flag when masked inactivity exceeds a configurable cycle count.

An 8-bit bang-bang thermostat controller with hysteresis for heating control.

Inserts configurable dead-time between complementary PWM signals and captures rising edges for sticky IRQ generation.

Measures input signal duty cycle as 8-bit percentage with sticky IRQ threshold comparison.

Edge Rate Limiter 8-bit with sticky IRQ capture and configurable threshold.

Enable-Gated Set/Reset Flag with priority clearing and hold state.

An 8-bit gated frequency counter supporting binary and Gray code parallel loading with IRQ generation on overflow.

8-bit Schmitt trigger with sticky interrupt capture and configurable hysteresis thresholds.

An 8-bit linear ramp generator with byte-enable control and sticky IRQ capture upon reaching 0xFF.

Detects absence of pulses within a defined window and latches a sticky IRQ flag.

Non-retriggerable one-shot pulse generator with sticky IRQ capture and configurable pulse width.

A configurable one-shot timer with hold capability and sticky interrupt capture logic.

An 8-bit period-based frequency meter that captures clock cycles between rising edges of an input signal. It features a sticky interrupt flag and a synchronous clear mechanism. The counter saturates at 255 to handle long periods.

Programmable one-shot pulse generator with rearm gap and sticky IRQ capture.

Measures high-pulse width on din and validates it against min/max thresholds with sticky fail flag.

A retriggerable one-shot pulse generator with configurable width and sticky interrupt capture.

Traffic-Light Controller FSM with sticky IRQ capture and emergency override.

Saturating up/down counter with fixed 8-bit limits and boundary flags.

A 16-word by 16-bit synchronous RAM with independent write/read clocks and 2-bit byte enable support. Features active-low reset and registered read output for timing closure.

16-word by 8-bit synchronous RAM with independent write/read clocks and registered read output. No reset logic included.

A configurable 32-bit asynchronous FIFO using AXI4-Stream interfaces and Gray code pointers for safe cross-clock-domain data transfer.

A 32-bit register with independent byte-write enables for partial updates.

32-word by 16-bit synchronous single-port RAM with combinational read.

A 4-deep by 8-bit wide register file with synchronous write and combinational read ports.

Four-word 8-bit single-port RAM with async reset clear, synchronous write, and combinational read.

256x64 dual-port RAM with byte-enable masking and combinational reads.

An 8-bit depth-1 skid buffer that absorbs backpressure by holding data until the consumer is ready. It asserts ready_in only when empty and maintains valid_out until valid_in deasserts.

8x16 Single-Port Synchronous RAM with byte write enable. Depth: 8 words, Width: 16 bits. Read is synchronous (data available on next clock edge after address). Write is synchronous (data written on rising edge if we_n is low).

An 8-deep, 32-bit wide register file with one synchronous write port and two independent combinational read ports.

8-bit wide, 8-depth synchronous single-port RAM with write-first read behavior and asynchronous reset.

Asymmetric RAM with 8-bit write, 16-bit read, byte-enable, and invalidate-to-shadow functionality.

8x32 register file with byte-enable write support and shadow commit mechanism for atomic updates.

A 4-entry, 8-bit Content-Addressable Memory with individual entry invalidate capability.

A synchronous circular buffer with 16 entries and 8-bit data width supporting push/pop operations with full/empty flags.

Single-clock FIFO that tracks occupancy with an explicit count register, exposes wready/rvalid on both producer and consumer sides, and defaults to depth 64 with 16-bit data.

A credit-based flow control module that manages ready/valid handshakes with a maximum of 4 credits.

Dual-Port RAM with write-first bypass on Port A and shadow buffer read with invalidation on Port B.

Dual-Port Register File 4x16 with Invalidate, Shadow Commit, Byte Enable, and Hazard Detection for L2 upgrades.

First-Word-Fall-Through synchronous FIFO with 16x8 depth and programmable almost-full/empty thresholds.

A First-Word-Fall-Through (FWFT) synchronous FIFO module with configurable almost full and almost empty threshold flags for precise flow control.

Synchronous LIFO stack with depth 8, 8-bit data width, full/empty flags, and overflow/underflow protection.

An 8x8 double-buffering module that swaps between two memory banks on a frame pulse for continuous data streaming.

Compact single-clock FIFO using extra-bit read/write pointers for full/empty detection, enable-style w_en/r_en ports, synchronous flush, and default depth 16 with 32-bit data.

True dual-clock 1-write-2-read register file with 8x16 depth and registered read output.

An 8x16 register file with shadow buffer support for speculative writes, atomic commit, and abort capabilities.

A registered Read-Only Memory with 64 words of 8 bits and an active-low output enable signal.

A combinational ROM with 16 words of 8 bits, mapping 4-bit addresses to their hex values.

Simple CAM 4-Entry x 8-Bit with search, write, and invalidate operations for L2 cache tag lookup.

A 2-deep skid buffer for 8-bit stream data that handles back-pressure and stalls.

A synchronous FIFO module with 64-bit data width, configurable depth, and status flags for full, empty, almost full, and almost empty conditions.

A synchronous FIFO depth calculator using a counter-based approach to track buffer levels with configurable almost-full thresholds.

True dual-port RAM with independent write and read clock domains, 8 words x 8 bits, synchronous reset.

4-word by 8-bit register file with write-priority, bit-masking, hold, and park controls.

A 1-bit GPIO pin driver that detects edge transitions and generates a sticky interrupt flag.

32-Bit MMIO GPIO with byte-strobed data output and sticky pin-change interrupt.

8-Bit GPIO Output Register with synchronous load and active-low reset

An 8-bit GPIO register with atomic Set and Clear operations where Clear takes priority over Set.

Register-mapped 8-bit GPIO with per-pin direction, data registers, and rising-edge interrupt generation.

Detects I2C arbitration loss by comparing driven and sampled SDA values. Outputs a sticky flag until cleared.

Detects I2C bus idle conditions based on SCL and SDA levels with configurable threshold.

Detects I2C clock stretching by counting SCL low cycles against a configurable threshold.

Detects I2C NACK conditions during the ACK phase and latches a sticky flag until reset.

Detects I2C Start and Stop conditions synchronously on the SCL rising edge.

Synthesizable IEEE 1149.1 JTAG TAP Controller with 32-bit DR and IR paths.

A lightweight I²C master controller supporting Standard Mode (100 kHz) with configurable clock parameters and basic transaction control.

A lightweight I²C slave controller that translates I²C read/write operations into simple register file transfers with clock stretching support.

Minimal SPI master for CPOL=0, CPHA=0, 8-bit transfers with start/done handshake.

SPI host/controller operating in CPOL=0 CPHA=0 with 8-bit shift frames.

SPI Mode-3 Slave (CPOL=1, CPHA=1) 8-Bit

Synthesizable SPI slave with ready/valid byte interface, LSB-first Mode 0 shifting, and chip-select framed transfers.

A registered sticky flag module with set and clear inputs where clear takes priority.

A synthesizable 8-N-1 UART with valid/ready TX/RX handshakes and parameterizable baud timing.

8N1 UART Core with Configurable Depth TX and RX FIFOs. Supports backpressure and interrupt-ready status flags.