What you practice
Out-of-order and interleaving: observe-only routing theory (3.5). See how transaction IDs support out-of-order read responses and interleaved write beats. It is in Out-of-Order and Interleaving — Part 3 · AXI4 Full RTL Design of the AXI Masterclass. Burst, outstanding, and a BRAM memory bridge.
AXI only counts when the handshake simulates. RTL Studio is the Verilog and SystemVerilog IDE where you edit the RTL and prove each beat on a VCD.
Run it in the Verilog IDE
- Open the lesson in the IDE and find the valid/ready or AXI channel ports in the editor.
- Simulate with Verilator. Confirm the beat on the VCD, not only in the transcript.
- Check that data moves only on the beats this lesson describes, and that backpressure holds the transfer.
- Synthesize the RTL master, slave, or buffer with Yosys. Leave the UVM bench out of synthesis.
The lesson is done when the simulation matches Out-of-order and interleaving: observe-only routing theory. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.