What you practice
Independent channel driver: fork/join_none on five AXI channels (4.2). Drive all five channels in parallel with fork/join_none to avoid deadlocks. It is in Independent Channel Driver — Part 4 · AXI4 Full UVM Verification of the AXI Masterclass. Five-channel parallel UVM for AXI Full timing.
AXI only counts when the handshake simulates. RTL Studio is the Verilog and SystemVerilog IDE where you edit the RTL and prove each beat on a VCD.
Run it in the Verilog IDE
- Open the lesson in the IDE and find the valid/ready or AXI channel ports in the editor.
- Simulate with Verilator. Confirm the beat on the VCD, not only in the transcript.
- Check that data moves only on the beats this lesson describes, and that backpressure holds the transfer.
- Synthesize the RTL master, slave, or buffer with Yosys. Leave the UVM bench out of synthesis.
The lesson is done when the simulation matches Independent channel driver: fork/join_none on five AXI channels. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.