What you practice
Multi-master arbiter RTL: round-robin grant logic (5.4). Implement round-robin arbitration for simultaneous master requests. It is in Multi-Master Arbitration RTL — Part 5 · SVA and System Integration of the AXI Masterclass. SVA protocol checkers, multi-master systems, and the capstone.
AXI only counts when the handshake simulates. RTL Studio is the Verilog and SystemVerilog IDE where you edit the RTL and prove each beat on a VCD.
Run it in the Verilog IDE
- Open the lesson in the IDE and find the valid/ready or AXI channel ports in the editor.
- Simulate with Verilator. Confirm the beat on the VCD, not only in the transcript.
- Check that data moves only on the beats this lesson describes, and that backpressure holds the transfer.
- Synthesize the RTL master, slave, or buffer with Yosys. Leave the UVM bench out of synthesis.
The lesson is done when the simulation matches Multi-master arbiter RTL: round-robin grant logic. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.