What you practice
Load/store control and byte enables (3.1). Implement per-byte write enable generation and data alignment logic for the RISC-V Load/Store Unit based on access size and address offset. It is in LSU control & byte_en — Part 3 · Load/Store & Local Memory of the RISC-V RV32I Core Masterclass.
The RV32I core is Verilog you simulate in the browser IDE. Verilator runs the program; the waveform shows PC, the instruction, and the register write.
Run it in the Verilog IDE
- Open the RV32I lesson in the IDE. Fetch, decode, and execute are source you can simulate.
- Run Verilator and watch PC, the instruction, and the register write on the waveform.
- Treat a program printout as done only after the ISA step this lesson names matches the wave.
- Change the RTL in the editor, rerun Verilator, and read the waveform again in the same tab.
The lesson is done when the simulation matches Load/store control and byte enables. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.