What you practice
mcause codes and the mtvec base (4.4). Program the trap vector base and read back interrupt versus exception causes in the RISC-V CSR module. It is in mcause & mtvec modes — Part 4 · CSR, Trap & IRQ Interface of the RISC-V RV32I Core Masterclass.
The RV32I core is Verilog you simulate in the browser IDE. Verilator runs the program; the waveform shows PC, the instruction, and the register write.
Run it in the Verilog IDE
- Open the RV32I lesson in the IDE. Fetch, decode, and execute are source you can simulate.
- Run Verilator and watch PC, the instruction, and the register write on the waveform.
- Treat a program printout as done only after the ISA step this lesson names matches the wave.
- Change the RTL in the editor, rerun Verilator, and read the waveform again in the same tab.
The lesson is done when the simulation matches mcause codes and the mtvec base. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.