5.1 · Stitch the single-cycle datapath — RISC-V Core Class

What you practice

Stitch the single-cycle datapath (5.1). Stitch the single-cycle datapath by connecting the RV32I core to instruction and data memories in student/rtl/design.sv and verify execution with the testbench. It is in Stitch fetch-exec-LSU — Part 5 · Core Capstone of the RISC-V RV32I Core Masterclass.

The RV32I core is Verilog you simulate in the browser IDE. Verilator runs the program; the waveform shows PC, the instruction, and the register write.

Run it in the Verilog IDE

Open the RV32I lesson in the IDE. Fetch, decode, and execute are source you can simulate.
Run Verilator and watch PC, the instruction, and the register write on the waveform.
Treat a program printout as done only after the ISA step this lesson names matches the wave.
Change the RTL in the editor, rerun Verilator, and read the waveform again in the same tab.

The lesson is done when the simulation matches Stitch the single-cycle datapath. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.