RTL Studio Open IDE

5.3 · RISC-V CLASS

Core testbench with a fibonacci loop

Preload a Fibonacci loop into the RV32I core's instruction memory and verify the computed result in debug_x10.

Video coming soon. This lesson page stays at the same URL when the lecture publishes.

What you practice

Core testbench with a fibonacci loop (5.3). Preload a Fibonacci loop into the RV32I core's instruction memory and verify the computed result in debug_x10. It is in Core TB: fibonacci loop — Part 5 · Core Capstone of the RISC-V RV32I Core Masterclass.

The RV32I core is Verilog you simulate in the browser IDE. Verilator runs the program; the waveform shows PC, the instruction, and the register write.

Run it in the Verilog IDE

  1. Open the RV32I lesson in the IDE. Fetch, decode, and execute are source you can simulate.
  2. Run Verilator and watch PC, the instruction, and the register write on the waveform.
  3. Treat a program printout as done only after the ISA step this lesson names matches the wave.
  4. Change the RTL in the editor, rerun Verilator, and read the waveform again in the same tab.

The lesson is done when the simulation matches Core testbench with a fibonacci loop. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.

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