RTL Studio Open IDE

1.1 · RV SYS CLASS

LSU AXI-Lite master

Implement the reset logic for an AXI4-Lite master FSM to initialize state and data registers for RISC-V load/store operations.

Video coming soon. This lesson page stays at the same URL when the lecture publishes.

What you practice

LSU AXI-Lite master (1.1). Implement the reset logic for an AXI4-Lite master FSM to initialize state and data registers for RISC-V load/store operations. It is in LSU to AXI-Lite master FSM — Part 1 · Core on Bus (MMIO) of the RISC-V on SoC & System Masterclass.

The core and the mini-SoC simulate as one workspace in the IDE. Follow MMIO, interrupts, and the program on the Verilator waveform, not only a pass line.

Run it in the Verilog IDE

  1. Open the system lesson in the IDE. The RV32I core and the mini-SoC fabric simulate together.
  2. Run Verilator and trace the program through MMIO: address, load/store data, and the peripheral response.
  3. Interrupts and DMA belong on the waveform next to the instruction stream, not only in a pass/fail line.
  4. Edit the integration RTL, resimulate, and run Yosys on the structural block when you want a netlist.

The lesson is done when the simulation matches LSU AXI-Lite master. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.

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