What you practice
Multi-periph sequence (2.5). Complete the testbench port connections and program load for a multi-peripheral RISC-V sequence to verify GPIO, UART, and timer interactions. It is in Multi-peripheral sequence — Part 2 · Peripheral Programs of the RISC-V on SoC & System Masterclass.
The core and the mini-SoC simulate as one workspace in the IDE. Follow MMIO, interrupts, and the program on the Verilator waveform, not only a pass line.
Run it in the Verilog IDE
- Open the system lesson in the IDE. The RV32I core and the mini-SoC fabric simulate together.
- Run Verilator and trace the program through MMIO: address, load/store data, and the peripheral response.
- Interrupts and DMA belong on the waveform next to the instruction stream, not only in a pass/fail line.
- Edit the integration RTL, resimulate, and run Yosys on the structural block when you want a netlist.
The lesson is done when the simulation matches Multi-periph sequence. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.