What you practice
System e2e TB (5.3). Drive the rv32_soc_top platform from a SystemVerilog testbench to verify end-to-end system behavior by instantiating the design and connecting all interface signals. It is in End-to-end system TB — Part 5 · System Capstone of the RISC-V on SoC & System Masterclass.
The core and the mini-SoC simulate as one workspace in the IDE. Follow MMIO, interrupts, and the program on the Verilator waveform, not only a pass line.
Run it in the Verilog IDE
- Open the system lesson in the IDE. The RV32I core and the mini-SoC fabric simulate together.
- Run Verilator and trace the program through MMIO: address, load/store data, and the peripheral response.
- Interrupts and DMA belong on the waveform next to the instruction stream, not only in a pass/fail line.
- Edit the integration RTL, resimulate, and run Yosys on the structural block when you want a netlist.
The lesson is done when the simulation matches System e2e TB. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.