What you practice
IRQ status / enable / clear (2.4). Implement sticky IRQ status, enable, and clear CSRs using AXI-Lite interface logic. It is in IRQ Status Enable Clear — Part 2 · Peripheral Islands of the SoC Masterclass. Build GPIO, timer, UART, and IRQ islands, then wrap them as a peripheral subsystem.
SoC lessons simulate the fabric and the peripheral together in the IDE. Verilator is the simulator; the waveform is where address and response show up.
Run it in the Verilog IDE
- Open the lesson workspace in the IDE. The fabric and the peripheral are one simulation.
- Run Verilator and follow the address, write data, and read response on the waveform.
- A passing log is not enough when decode or an IRQ line is the point of the lesson — those show up on the VCD.
- Run Yosys on the RTL island you just integrated when you want the mapped cells.
The lesson is done when the simulation matches IRQ status / enable / clear. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.