What you practice
Fixed master CPU stub (5.1). Implement a fixed master CPU stub FSM to drive AXI write transactions for GPIO and timer programming. It is in CPU Stub Master — Part 5 · Integration & Capstone of the SoC Masterclass. Tie a CPU stub, decode, peripherals, DMA, and IRQ into a mini-SoC capstone.
SoC lessons simulate the fabric and the peripheral together in the IDE. Verilator is the simulator; the waveform is where address and response show up.
Run it in the Verilog IDE
- Open the lesson workspace in the IDE. The fabric and the peripheral are one simulation.
- Run Verilator and follow the address, write data, and read response on the waveform.
- A passing log is not enough when decode or an IRQ line is the point of the lesson — those show up on the VCD.
- Run Yosys on the RTL island you just integrated when you want the mapped cells.
The lesson is done when the simulation matches Fixed master CPU stub. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.