CDV: hit FIFO full and reach 100% coverage

What you practice

CDV: hit FIFO full and reach 100% coverage (3.6). Tune sequence constraints to flood writes until the FIFO-full coverpoint hits and LCOV reaches 100%. It is in CDV mission — Part 3 · Env and Coverage of the UVM Masterclass. Assemble the verification environment, compare data, and hunt coverage.

The UVM bench compiles in that same browser SystemVerilog simulator. You edit the test in the IDE, run Verilator, and read the log beside the waveform.

Run it in the Verilog IDE

1. Open the UVM workspace in the IDE. The DUT and the testbench compile together in the browser.
2. Run the SystemVerilog simulation with Verilator and read the phase and scoreboard lines in the log.
3. When the check is on pins rather than a print, open the VCD next to that log.
4. Edit the sequence, driver, or scoreboard in the IDE and rerun. You stay in the same simulator.

The lesson is done when the simulation matches CDV: hit FIFO full and reach 100% coverage. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.