RTL Studio Open IDE

5.1 · UVM CLASS

AMBA APB: PSEL, PENABLE, PWRITE timing

Learn APB SETUP/ACCESS timing and verify slave behavior in simulation.

Video coming soon. This lesson page stays at the same URL when the lecture publishes.

What you practice

AMBA APB: PSEL, PENABLE, PWRITE timing (5.1). Learn APB SETUP/ACCESS timing and verify slave behavior in simulation. It is in APB protocol — Part 5 · AMBA APB and UVM RAL of the UVM Masterclass. APB protocol, register abstraction, and the roadmap to AXI.

The UVM bench compiles in that same browser SystemVerilog simulator. You edit the test in the IDE, run Verilator, and read the log beside the waveform.

Run it in the Verilog IDE

  1. Open the UVM workspace in the IDE. The DUT and the testbench compile together in the browser.
  2. Run the SystemVerilog simulation with Verilator and read the phase and scoreboard lines in the log.
  3. When the check is on pins rather than a print, open the VCD next to that log.
  4. Edit the sequence, driver, or scoreboard in the IDE and rerun. You stay in the same simulator.

The lesson is done when the simulation matches AMBA APB: PSEL, PENABLE, PWRITE timing. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.

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