What you practice
Mission: reg_model frontdoor write() one-liner (5.4). Control APB registers with a single RAL frontdoor write() instead of raw bus sequences. It is in Frontdoor — Part 5 · AMBA APB and UVM RAL of the UVM Masterclass. APB protocol, register abstraction, and the roadmap to AXI.
The UVM bench compiles in that same browser SystemVerilog simulator. You edit the test in the IDE, run Verilator, and read the log beside the waveform.
Run it in the Verilog IDE
- Open the UVM workspace in the IDE. The DUT and the testbench compile together in the browser.
- Run the SystemVerilog simulation with Verilator and read the phase and scoreboard lines in the log.
- When the check is on pins rather than a print, open the VCD next to that log.
- Edit the sequence, driver, or scoreboard in the IDE and rerun. You stay in the same simulator.
The lesson is done when the simulation matches Mission: reg_model frontdoor write() one-liner. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.