RTL Studio Open IDE

1.5 · AXI CLASS

Skid buffer: decouple VALID/READY timing on an AXI channel

Add a skid buffer on the write data channel to break VALID/READY timing paths under backpressure.

Video coming soon. This lesson page stays at the same URL when the lecture publishes.

What you practice

Skid buffer: decouple VALID/READY timing on an AXI channel (1.5). Add a skid buffer on the write data channel to break VALID/READY timing paths under backpressure. It is in Skid Buffer — Part 1 · AXI4-Lite RTL Design of the AXI Masterclass. Design an AXI4-Lite slave in pure SystemVerilog.

AXI only counts when the handshake simulates. RTL Studio is the Verilog and SystemVerilog IDE where you edit the RTL and prove each beat on a VCD.

Run it in the Verilog IDE

  1. Open the lesson in the IDE and find the valid/ready or AXI channel ports in the editor.
  2. Simulate with Verilator. Confirm the beat on the VCD, not only in the transcript.
  3. Check that data moves only on the beats this lesson describes, and that backpressure holds the transfer.
  4. Synthesize the RTL master, slave, or buffer with Yosys. Leave the UVM bench out of synthesis.

The lesson is done when the simulation matches Skid buffer: decouple VALID/READY timing on an AXI channel. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.

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