RTL Studio Open IDE

2.3 · AXI CLASS

AXI monitor and scoreboard: sample bus and compare registers

Passively sample the bus and verify register reads/writes with monitor and scoreboard.

Video coming soon. This lesson page stays at the same URL when the lecture publishes.

What you practice

AXI monitor and scoreboard: sample bus and compare registers (2.3). Passively sample the bus and verify register reads/writes with monitor and scoreboard. It is in AXI Monitor and Scoreboard — Part 2 · AXI4-Lite UVM Verification of the AXI Masterclass. Verify the AXI4-Lite DUT with UVM and RAL.

AXI only counts when the handshake simulates. RTL Studio is the Verilog and SystemVerilog IDE where you edit the RTL and prove each beat on a VCD.

Run it in the Verilog IDE

  1. Open the lesson in the IDE and find the valid/ready or AXI channel ports in the editor.
  2. Simulate with Verilator. Confirm the beat on the VCD, not only in the transcript.
  3. Check that data moves only on the beats this lesson describes, and that backpressure holds the transfer.
  4. Synthesize the RTL master, slave, or buffer with Yosys. Leave the UVM bench out of synthesis.

The lesson is done when the simulation matches AXI monitor and scoreboard: sample bus and compare registers. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.

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