RTL Studio Open IDE

4.5 · AXI CLASS

AXI virtual sequence: parallel read and write traffic

Fork parallel AXI read and write sequences to stress outstanding transaction handling.

Video coming soon. This lesson page stays at the same URL when the lecture publishes.

What you practice

AXI virtual sequence: parallel read and write traffic (4.5). Fork parallel AXI read and write sequences to stress outstanding transaction handling. It is in AXI Virtual Sequence — Part 4 · AXI4 Full UVM Verification of the AXI Masterclass. Five-channel parallel UVM for AXI Full timing.

AXI only counts when the handshake simulates. RTL Studio is the Verilog and SystemVerilog IDE where you edit the RTL and prove each beat on a VCD.

Run it in the Verilog IDE

  1. Open the lesson in the IDE and find the valid/ready or AXI channel ports in the editor.
  2. Simulate with Verilator. Confirm the beat on the VCD, not only in the transcript.
  3. Check that data moves only on the beats this lesson describes, and that backpressure holds the transfer.
  4. Synthesize the RTL master, slave, or buffer with Yosys. Leave the UVM bench out of synthesis.

The lesson is done when the simulation matches AXI virtual sequence: parallel read and write traffic. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.

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