SVA basics for AXI: stable data while VALID waits for READY

What you practice

SVA basics for AXI: stable data while VALID waits for READY (5.1). Enforce handshake stability: data and control remain stable while VALID is high and READY is low. It is in SVA Basics for AXI — Part 5 · SVA and System Integration of the AXI Masterclass. SVA protocol checkers, multi-master systems, and the capstone.

AXI only counts when the handshake simulates. RTL Studio is the Verilog and SystemVerilog IDE where you edit the RTL and prove each beat on a VCD.

Run it in the Verilog IDE

1. Open the lesson in the IDE and find the valid/ready or AXI channel ports in the editor.
2. Simulate with Verilator. Confirm the beat on the VCD, not only in the transcript.
3. Check that data moves only on the beats this lesson describes, and that backpressure holds the transfer.
4. Synthesize the RTL master, slave, or buffer with Yosys. Leave the UVM bench out of synthesis.

The lesson is done when the simulation matches SVA basics for AXI: stable data while VALID waits for READY. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.