What you practice
Read/write permission gates (1.5). Implement read/write permission gates and assert SLVERR on access violations. It is in RW Permission Gates — Part 1 · Address Map & Decode of the SoC Masterclass. Turn a memory map into combinational decode, one-hot selects, and an AXI-Lite fabric.
SoC lessons simulate the fabric and the peripheral together in the IDE. Verilator is the simulator; the waveform is where address and response show up.
Run it in the Verilog IDE
- Open the lesson workspace in the IDE. The fabric and the peripheral are one simulation.
- Run Verilator and follow the address, write data, and read response on the waveform.
- A passing log is not enough when decode or an IRQ line is the point of the lesson — those show up on the VCD.
- Run Yosys on the RTL island you just integrated when you want the mapped cells.
The lesson is done when the simulation matches Read/write permission gates. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.