RTL Studio Open IDE

1.6 · SOC CLASS

Multi-slave interconnect lite

Integrate the timer CSR slave with the multi-slave interconnect by implementing address decoding and register read/write logic.

Video coming soon. This lesson page stays at the same URL when the lecture publishes.

What you practice

Multi-slave interconnect lite (1.6). Integrate the timer CSR slave with the multi-slave interconnect by implementing address decoding and register read/write logic. It is in Multi-Slave Interconnect — Part 1 · Address Map & Decode of the SoC Masterclass. Turn a memory map into combinational decode, one-hot selects, and an AXI-Lite fabric.

SoC lessons simulate the fabric and the peripheral together in the IDE. Verilator is the simulator; the waveform is where address and response show up.

Run it in the Verilog IDE

  1. Open the lesson workspace in the IDE. The fabric and the peripheral are one simulation.
  2. Run Verilator and follow the address, write data, and read response on the waveform.
  3. A passing log is not enough when decode or an IRQ line is the point of the lesson — those show up on the VCD.
  4. Run Yosys on the RTL island you just integrated when you want the mapped cells.

The lesson is done when the simulation matches Multi-slave interconnect lite. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.

Open in IDE Course playlist