What you practice
Reset sequencing (3.1). Implement a reset sequencer that stretches POR for a configurable number of cycles before releasing system and peripheral resets. It is in Reset Sequencing — Part 3 · System Control of the SoC Masterclass. Sequence reset, clock enables, boot vector, and watchdog into a sysctrl block.
SoC lessons simulate the fabric and the peripheral together in the IDE. Verilator is the simulator; the waveform is where address and response show up.
Run it in the Verilog IDE
- Open the lesson workspace in the IDE. The fabric and the peripheral are one simulation.
- Run Verilator and follow the address, write data, and read response on the waveform.
- A passing log is not enough when decode or an IRQ line is the point of the lesson — those show up on the VCD.
- Run Yosys on the RTL island you just integrated when you want the mapped cells.
The lesson is done when the simulation matches Reset sequencing. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.