RTL Studio Open IDE

3.2 · SOC CLASS

Clock enables & gating intro

Generate a clock enable signal from an idle indication to reduce power consumption.

Video coming soon. This lesson page stays at the same URL when the lecture publishes.

What you practice

Clock enables & gating intro (3.2). Generate a clock enable signal from an idle indication to reduce power consumption. It is in Clock Enables — Part 3 · System Control of the SoC Masterclass. Sequence reset, clock enables, boot vector, and watchdog into a sysctrl block.

SoC lessons simulate the fabric and the peripheral together in the IDE. Verilator is the simulator; the waveform is where address and response show up.

Run it in the Verilog IDE

  1. Open the lesson workspace in the IDE. The fabric and the peripheral are one simulation.
  2. Run Verilator and follow the address, write data, and read response on the waveform.
  3. A passing log is not enough when decode or an IRQ line is the point of the lesson — those show up on the VCD.
  4. Run Yosys on the RTL island you just integrated when you want the mapped cells.

The lesson is done when the simulation matches Clock enables & gating intro. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.

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