package and import

What you practice

package and import (1.9). Define and import packages to centralize shared types and constants across design and testbench. It is in Packages — Part 1 · Design in SV of the SystemVerilog Masterclass. Synthesizable SystemVerilog that removes Verilog ambiguity and cuts boilerplate.

The same IDE is the SystemVerilog simulator. Slang lints the file, Verilator runs it, and the waveform viewer sits next to the source.

Run it in the Verilog IDE

1. Open the lesson in the IDE. The SystemVerilog for this topic is already in the editor.
2. Lint with Slang before you simulate. It covers both Verilog and SystemVerilog in this IDE.
3. Run Verilator and inspect the VCD. Interfaces, classes, and assertions count only if the simulator agrees.
4. Run Yosys when the lesson is synthesizable RTL, and keep testbench-only constructs out of that module.

The lesson is done when the simulation matches package and import. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.