RTL Studio Open IDE

Wiki SystemVerilog Packages

Packages

Shared types and constants with import, without textual macros.

A package is a scope for typedef, localparam, and functions that many modules share. import pkg::* (or explicit names) beats `include soup.

flowchart TB
  pkg[pkg] --> rtl[rtl_modules]
  pkg --> tb[testbench]
package alu_pkg;
  typedef enum logic [1:0] { OP_ADD, OP_SUB, OP_AND, OP_OR } op_e;
endpackage

import alu_pkg::op_e;

Wrong vs right

Wrong — the same enum copy-pasted into DUT and TB until they diverge.

Right — one package, imported on both sides.

See also