0.1 · Hello UVM: macros and uvm_info — UVM Class

What you practice

Hello UVM: macros and uvm_info (0.1). Introduce UVM logging with uvm_info in a console-first testbench without UVM components. It is in Hello UVM — Part 0 · UVM Warming Up of the UVM Masterclass. How SystemVerilog classes evolve into the UVM verification framework.

The UVM bench compiles in that same browser SystemVerilog simulator. You edit the test in the IDE, run Verilator, and read the log beside the waveform.

Run it in the Verilog IDE

Open the UVM workspace in the IDE. The DUT and the testbench compile together in the browser.
Run the SystemVerilog simulation with Verilator and read the phase and scoreboard lines in the log.
When the check is on pins rather than a print, open the VCD next to that log.
Edit the sequence, driver, or scoreboard in the IDE and rerun. You stay in the same simulator.

The lesson is done when the simulation matches Hello UVM: macros and uvm_info. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.