Time master: UVM phase schedule

What you practice

Time master: UVM phase schedule (0.2). Implement build, connect, run, and report phases in a test class and observe execution order. It is in Hello UVM — Part 0 · UVM Warming Up of the UVM Masterclass. How SystemVerilog classes evolve into the UVM verification framework.

The UVM bench compiles in that same browser SystemVerilog simulator. You edit the test in the IDE, run Verilator, and read the log beside the waveform.

Run it in the Verilog IDE

1. Open the UVM workspace in the IDE. The DUT and the testbench compile together in the browser.
2. Run the SystemVerilog simulation with Verilator and read the phase and scoreboard lines in the log.
3. When the check is on pins rather than a print, open the VCD next to that log.
4. Edit the sequence, driver, or scoreboard in the IDE and rerun. You stay in the same simulator.

The lesson is done when the simulation matches Time master: UVM phase schedule. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.