What you practice
Analysis port: broadcast monitored data (2.5). Use analysis ports to broadcast monitored transactions to downstream components. It is in Analysis port — Part 2 · Agent: Driver & Monitor of the UVM Masterclass. Connect software UVM components to hardware FIFO pins.
The UVM bench compiles in that same browser SystemVerilog simulator. You edit the test in the IDE, run Verilator, and read the log beside the waveform.
Run it in the Verilog IDE
- Open the UVM workspace in the IDE. The DUT and the testbench compile together in the browser.
- Run the SystemVerilog simulation with Verilator and read the phase and scoreboard lines in the log.
- When the check is on pins rather than a print, open the VCD next to that log.
- Edit the sequence, driver, or scoreboard in the IDE and rerun. You stay in the same simulator.
The lesson is done when the simulation matches Analysis port: broadcast monitored data. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.