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Wiki UVM TLM ports

TLM ports

analysis / seq_item ports connect components without hard hierarchy.

UVM TLM ports are typed mailboxes: seq_item_port / seq_item_export between sequencer and driver; analysis_port from monitor to subscribers.

flowchart LR
  sqr[sequencer] -->|seq_item| drv[driver]
  mon[monitor] -->|analysis| sb[scoreboard]
  mon --> cov[coverage]

connect_phase is where drv.seq_item_port.connect(sqr.seq_item_export) (direction depends on the port kind — match the cookbook for your UVM version).

Wrong vs right

Wrong — new a scoreboard inside the driver and call it directly.

Right — monitor writes an analysis port; any number of subscribers bind in connect_phase.

See also