What you practice
Understanding Buses (1.2). Declare multi-bit buses and assign hexadecimal literals in Verilog. It is in Data Types — Part 1 · Verilog Core Syntax of the Verilog Masterclass. Language mechanics first — confirm behavior on waveforms, not big designs yet.
RTL Studio is a browser Verilog IDE and simulator. This free lesson runs there: the editor, Slang lint, Verilator, a VCD waveform viewer, and Yosys, with nothing to install.
Run it in the Verilog IDE
- Open this lesson in the IDE. The workspace is the Verilog module and its testbench.
- Edit the RTL so it matches the lesson goal, then lint it with Slang.
- Run the in-browser Verilator simulation. Read the log, then open the VCD in the waveform viewer.
- When the block is structural RTL, run Yosys in the same tab and compare the mapped cells with the behavior you just simulated.
The lesson is done when the simulation matches Understanding Buses. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.