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Wiki Verilog language Buses and literals

Buses and literals

Multi-bit vectors, sized literals, and concatenation.

A bus is a packed vector. Width and literal size are part of the spec — unsized 'hF is a foot-gun.

flowchart LR
  b7["[7]"] --> pack[packed_bus]
  b0["[0]"] --> pack
  pack --> hex["8'hA5"]
logic [7:0] data;
assign data = 8'hA5;
assign word = {data, 8'h00};   // concat → 16 bits
assign nibble = data[3:0];

Literals

Form Meaning
8'hA5 8-bit hex
4'b1101 4-bit binary
8'd13 8-bit decimal
'0 / '1 (SV) fill zeros / ones

Unsized 32 is at least 32 bits; mix it with a narrow LHS and you get silent truncation.

Wrong vs right

Wrong — concatenate without counting:

assign out8 = {a8, b8};  // 16 bits into 8

Right — size the LHS or slice:

assign out16 = {a8, b8};

See also