UVM sequence item and uvm_field macros

What you practice

UVM sequence item and uvm_field macros (1.1). Define a FIFO sequence item and register fields with uvm_field macros for copy, compare, and print. It is in Sequence Item — Part 1 · Stimulus Generation of the UVM Masterclass. Create randomized transactions and deliver them safely to the DUT.

The UVM bench compiles in that same browser SystemVerilog simulator. You edit the test in the IDE, run Verilator, and read the log beside the waveform.

Run it in the Verilog IDE

1. Open the UVM workspace in the IDE. The DUT and the testbench compile together in the browser.
2. Run the SystemVerilog simulation with Verilator and read the phase and scoreboard lines in the log.
3. When the check is on pins rather than a print, open the VCD next to that log.
4. Edit the sequence, driver, or scoreboard in the IDE and rerun. You stay in the same simulator.

The lesson is done when the simulation matches UVM sequence item and uvm_field macros. Change the source, run the Verilog simulator again, and read the waveform without leaving the IDE. Simulation guide · Yosys guide.