Wiki RISC-V Fetch, decode, execute

Fetch, decode, execute

PC+4 fetch, field decode, and a single-cycle or pipelined execute.

A teaching core is three ideas: PC (and IMEM), decode, execute / writeback. Load/store adds a DMEM port; branches redirect the PC.

flowchart LR
  pc[PC] --> imem[IMEM]
  imem --> dec[decode]
  dec --> ex[ALU]
  ex --> rf[regfile]
  rf --> ex

PC resets to a known address and otherwise does PC+4, unless a branch/jalr wins.

Wrong vs right

Wrong — write the register file in the same combo cloud that reads rs1 without a defined WB mux (sim races).

Right — explicit WB mux and a clocked regfile write enable. See Pipelines if you split F/D/E.