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Wiki Verilog language Concatenation

Concatenation

Pack fields into wider buses with {} and replication.

{a, b} glues bits left-to-right into a wider vector. Replication {n{x}} repeats x n times.

flowchart LR
  hi[a] --> cat["{a, b}"]
  lo[b] --> cat
  cat --> bus[wider_bus]
wire [7:0] byte = {nib_hi, nib_lo};   // 4+4
wire [15:0] sext = {{8{d[7]}}, d};    // sign-extend

Part selects must add up to the declared width. Nested concatenations are fine; unsized literals inside {} are not.

Wrong vs right

Wrong — {a, 1} with an unsized 1 (width is ambiguous).

Right — {a, 1'b1} or {a, 1'b0}.

See also