Every directed test starts the same way: a free-running clock, a held reset, then stimulus. #delay belongs only in the testbench.
sequenceDiagram participant rst as rst_n participant clk as clk rst->>rst: assert 0 clk->>clk: toggle rst->>rst: release 1 Note over rst,clk: then drive inputs
Pattern
initial clk = 1'b0;
always #5 clk = ~clk;
initial begin
rst_n = 1'b0;
// idle DUT inputs here
repeat (4) @(posedge clk);
rst_n = 1'b1;
end
Hold reset for several posedges so async-reset flops and reset synchronizers actually see it.
Wrong vs right
Wrong — poke data while reset is still low, then check:
rst_n = 0;
din = 8'hA5;
@(posedge clk);
assert (q == 8'hA5);
Right — release, wait a cycle (or two), then check the first real result.
Waves
Keep $dumpfile("sim/dump.vcd") + $dumpvars in the TB so RTL Studio can open Surfer. See the simulation guide.