RTL Studio Open IDE

Wiki Verilog language Operators

Operators

Arithmetic, bitwise, and logical operators in continuous assignments.

Combinational RTL is mostly operators on wires. Prefer assign (or always_comb) so the expression is a pure function of the inputs.

flowchart LR
  a[A] --> op["+  &  |  ^"]
  b[B] --> op
  op --> y[Y]
Kind Examples Notes
Arithmetic +, - Width follows the widest operand; watch overflow
Bitwise &, \|, ^, ~ Bit-for-bit
Reduction &a, \|a, ^a Collapse a vector to one bit
Logical &&, \|\|, ! 1-bit true/false, not bitwise
assign sum = a + b;
assign y   = a & b;
assign xor_all = ^data;

Wrong vs right

Wrong — mix logical && when you meant bitwise & on a bus.

Right — bitwise for datapath bits; logical only in if conditions.

See also